The SD card DAT3 line doesn’t need a pullup resistor on G120E? COM port doesn’t need one either? Are those integral to the SOM or just not needed now? Would be helpful to know what pins on the SoM have pullup / pulldown already installed in case I plan to use them as a GPIO.
(Don’t have a dev board, first test of anything will be a G120E SoM on a produced prototype PCB so can’t really test in advance easily)
Also for using SPI on G120 which is shared with internal flash, the datasheet documentation says the use of CS lines are required (no problem), but what is used for CS for the internal flash and how do I know if it is active or not? Is there a pin I can read the state of to determine if that is being used? Pulling a CS line low to use an SPI device on the same bus without knowing if the other is already active for internal flash is not good.
Can’t speak to the G120E problem, but I did encounter that shared SPI problem. In my case I had used the shared SPI (which is SPI2 btw) to communicate with a L6470. It would prevent the G120 from even booting, so I stay away from the G120’s SPI2 in my designs now.
That thread looks like it’s G30? This a common problem with all STM’s? G120 is not an STM32 though.
I’m waiting on my (fixed) boards to show up for the G30 so I haven’t got that far in testing, but I’m using SPI1 for a front panel header display + ethernet, and SPI2 for add-on modules. Hoping I don’t run in to issues there. Would be a pretty big rework to change it over to only use SPI1 (if even possible…)
On the G120, vs. G120E, G120 has an additional SPI3 bus. Does that suffer the same issues as G120E’s SPI2? I’m still at the schematic level in that G120 design so changes are less painful.
All needed pull ups and other circuitry are discussed on the pinout and design considerations in the datasheet. Neither SD DAT3 nor any COM port are specified as needing any resistors. Any pin that is given a name can be used as gpio without issue.
You cannot sample the SPI dataflash CS pin. If you use the NETMF or TinyCLR SPI interfaces, the bus access arbitration is automatically handled for you. There won’t be conflicts. You need to make sure that the SPI device connected to the bus does not force any state on any of the SPI pins if it is not selected. Doing so can cause issues, such as failing to boot. Of course, if you can use one of the other SPI busses, that is preferred.
Ok. With G30 and G80 there was a requirement for pullup resistors specified for COM1 RX and SD DAT3; why is this different on G120 / G400? I figured it was due to GHI placing pull-ups on the SoM board for those. Is that handled through an external resistor on the SoM or is that handled through an internal pull-up?
Which raises the question, if there is already an external pull-up resistor on the lines, it could cause issues if the pins are used for GPIO; if a pull down were added (either internal pull down via code or external pull down via resistor), and that pin which was already in a pull up state you’d just create a voltage divider and consume power needlessly, right?
G30 and G80 are based on a different processor family, so there are different requirements. One big difference is the bootup process – each processor samples a different set of pins in different circumstances.
A quick review of the G120E shows the only resistors on external pins are on USBH, USBC, Ethernet, SD_PWR, reset, and SPI2 MISO (for the data flash). COM1 RX, SD DAT3, and all other GPIO have no pull-ups on the G120E.
In the datasheet is says that no traces or vias should be placed under the G120/E.
That thing eats up a lot of real estate.
On a 4 layer board is it OK to run back side traces (no vias)? Does this recommendation for no traces only apply to the front side? I’ll have a ground and Vcc plane and a bare top signal plane, only traces will be on the reverse.
Is the concern due to the crystal circuits causing interference or some other reason?
Is the “no trace/via under SoM” due to crystals or due to needing a flat mounting surface for soldering the SoM?
Would traces on the back signal plane be OK? With Vcc and GND planes in between top and bottom signal layers on a 4 layer board should help isolate the signals from any interference from crystals or high speed SPI paths?
We looked into this. It is not recommended to route under the SoM (i.e. route on the top layer) because of the possibility of poor solder mask shorts. If the board house does not apply the solder mask well, top layer traces/vias exposed on your board and bottom layer traces/vias exposed on our SoMs could inadvertently connect, thus shorting the circuit.
If you are comfortable with the quality of the solder mask from your board house, then it should be okay to route under the SoM.