Why 2 crystals (Q1 & Q3) in the CERB40?

NETMF & Gadgeteer
1

Hello,

I don’t undestand why there are 2 crystals (Q1 & Q3) in the CERB40 design.

What is this Q3 “dnp” crystal that i cannot see in any other designs ?
Would that work without it ?

Thanks,

Xavier

2

Q1 is the main crystal that the Processor needs to run correctly.
Q3 is the crystal for the RTC which only needs to be there if you need the RTC functionality. The design will run fine without Q3.

3

Thanks Bill for your answer.
But you’re talking about Q2 the RTC crystal.

Q3 is in parallel with Q1.
Give a look at the schema :
http://www.ghielectronics.com/downloads/schematic/FEZ_Cerb40_II_SCH.pdf

On the CERB40 it seems to be under the usual quartz.

So ??

4

Sorry, didn’t bother to look at the sch…
Ignore Q3, I would assume it’s a different footprint or something…

5

DNP is “do not populate”. Designers often place alternate parts on the schematic and or the PCB layout to allow alternate footprints or supplier (manufacturer) parts of the same value.

You can avoid the DNP part on your design.

6

Dnp = “do not populate” ? Good to know :wink:
And thanks both of you for you answer.

Do you know what is the Q1 quartz reference used in the CERB40 ?
The partlist with eagle tells me : CRYTALSM49

What model can i use so that it works with the associated 2 x 27pF load capacitors ?
Does any crystal with a load capacitance of 18pF work ?

The 27pF seems a bit higher than other design (18pF or 20pF most of the time), is it because of the small size of the board which has a low stray capacitance ?
( Choosing the Right Crystal and Caps for your Design « Adafruit Industries – Makers, hackers, artists, designers and engineers! )

Thanks,

Xavier

7

You should read the St micro datasheet for the processor yourself for their design tips on this… dont listen to us! :slight_smile:

8

Thanks Brett.

From 5.3.8 of the datashhet :
“The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.”.

So for a crystal with 18 pF load capacitance and with the suggested 10pF for MCU/PCB that makes CL1 = CL2 = 182 - 102 = 16 pF.

I’m even more surprised by the choice of the 27pF in the CERB40.
Do i miss something ?

9

There have been several discussions on this topic in the past. The short version is that they’re almost certainly wrong, but it may work without changing them out, or it may not.

10

@ Ixox - Here is the information you are looking for:

https://www.ghielectronics.com/community/forum/topic?id=8447

Also, the “Cerb40 II” has the caps and crystal integrated, so there is nothing to do if you just buy that. I would recommend that.