Main Site Documentation

WatchDog Reset


#1

Is it possible to cause the watchdog to set a pin high when it’s resetting the device? I want to alert the rest of the electronics that the uC has been reset.


#2

The watchdog can tell you if the last reset was normal or a watchdog reset.
Then you can inform your peripherial hardware.


#3

So, let the firmware inform the hardware; and let that be the very first thing that the firmware does.


#4

I was not aware of this. Do you think that’s available in the STM32F405 (Cerb-Family) CPU as well? I might have to go digging into the CPU docs to see if I can implement that. Hopefully, I just have to read a bit out of one of the registers or something.

It’s always been a fear of mine that the device gets into some infinite loop of rebooting itself with the watchdog. This flag could allow me to start in a “safe” mode if the watchdog was the cause of the reboot…


#5

@ Valkrie, you’ve read my mind.


#6

It’s a property in the Watchdog class:
Premium 4.2: GHI.Premium.Hardware.LowLevel.Watchdog.LastResetCause
OSHW 4.2: ?
4.3: GHI.Processor.Watchdog.LastResetCause
Most/Some processors store the reset cause in a register you can read back.


#7

I saw this in Codeshare,

https://www.ghielectronics.com/community/codes

You could then set a pin high before shutting down.


#8

@ stevepx - Is this what you are referring to? https://www.ghielectronics.com/community/codeshare/entry/888


#9

Looks like it should be easy. From the STM32F405 docs:

[quote]
A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see Figure 4).
A system reset is generated when one of the following events occurs:

  1. A low level on the NRST pin (external reset)
  2. Window watchdog end of count condition (WWDG reset)
  3. Independent watchdog end of count condition (IWDG reset)
  4. A software reset (SW reset) (see Software reset)
  5. Low-power management reset (see Low-power management reset)
    Software reset
    The reset source can be identified by checking the reset flags in the RCC clock control &
    status register (RCC_CSR).

Bit 29 IWDGRSTF: Independent watchdog reset flag
This bit is set by hardware when an independent watchdog reset from VDD domain occurs.
Cleared by writing to the RMVF bit.
0: No watchdog reset occurred
1: Watchdog reset occurred [/quote]


#10

@ Valkyrie, Then that means the pins will be in a guaranteed state on the Cerb devices upon watchdog reset?


#11

Not sure what you mean… The reset flag gets set and appears to stay set until it is cleared. I don’t know if they accumulate or not. When I say accumulate, I mean the flags all start at 0, but when you reset a flag gets set to 1. Then if you reset a different way, the first flag stays 1 and the other corresponding flag gets set to 1…? I dunno.

But in any case, I added this reset state checking to my codeshare for the Watchdog timer. You can find it here: https://www.ghielectronics.com/community/codeshare/entry/809

Look at the usage sample for how to use it.

The watchdog state looks right, but I don’t know about the others.