Understanding my Saleae Logic Analyzer

I’ll go with he didn’t clean some conductive flux of the board and a high current is being allowed to pass between master out and ground resulting in an undervoltage on the pin.

Thanks for all the input. I’ll look it over again but I’ve looked it over several times with a magnifying glass and 5 of these were assembled and none of them work. Of course, they were all baked at the same time. Maybe they just needed to stay in the oven a bit longer.

@ ianlee74 - How did you test them after reflow (I’m assuming by baked you meant reflow).

That’s the exercise we’re currently going through :wink: But, if you’re question is more along the lines of how I tested the traces then I can say that I didn’t yet test every trace only those that appeared suspect under magnification.

I think I found your problem or at least an issue with your design.

Pin 20 is VDD and you don’t have this connected to power. It simply goes to C2. I can’t see any other connection and the track labeling shows it as only to the cap.


Dave McLaughlin, has one fine set of eyes! I agree 100% with him.
scratch the mask off pin 20’s foil and solder a jumper to pin 19’s via right next door.

Great catch Dave!!!

DOH!!! Can’t believe I missed that! I’m firing up my iron right now. Maker Faire will have to wait! :smiley:

Even easier. A jumper wire across C1 and C2 will do it.

Even easier…stick a wire in the via and solder the other end to C2 :smiley:

Check out that nice high signal now! Still a little noisy but probably OK. The driver isn’t giving me what I expect yet but I suspect that’s from me monkeying around with it too much. Let me compare to the original driver and I’ll bet we’re in business! Good catch, Dave. Thanks!

While I’m debugging the driver… Now I have a question related to my original post. First, I want to say that having the analog capture on this analyzer is just fantastic. I was using an Logic Sniffer by Open Logic previously and it didn’t have that. Being able to see the analog signal next to the logic signal makes understanding a whole lot easier. However, back to my question… The software seems to count any little blip around 1V as a signal when drawing the square wave but it correctly doesn’t count it in the binary (see MISO). Something definitely seems out of sync here within the software. Is there a way to configure the trigger voltage level when drawing the square wave? I guess its time to post this question to Saleae.

If you look at the specs for the Logic 8, it has a fixed high level of 1.2v. The Pro line is selectable. The 4, has a higher, but still fixed level. Do you have the time domain reconstruction filter on or off? It looks like it is trying to make everything look like a sine wave and does not have enough points to give you a real representation of the signal.

The datasheet for the MAX part indicates the data out of the part is tri-stated when the master writes the address, i.e. it uses half-duplex communication. So, what you are seeing is coupling into MISO from both SCLK and MOSI. The logic part doesn’t see a high at the transition of the clock because the signal is below the threshold at that point in time. That is why I said your signal was not to spec in the logic domain. It is even less to spec in the time domain :slight_smile:

If you look at the specs for the Logic 8, it has a fixed high level of 1.2v. The Pro line is selectable. The 4, has a higher, but still fixed level.[/quote]
I missed that. Still it seems odd to me that the SPI analyzer recognizes one level and the graph another.

I wasn’t really aware of this option but it turns out it is on by default. I turned it off but I can’t really see a difference. See attached.

At this late hour, its taking me a bit to digest that… However, I have confirmed that my SPI config is indeed requesting 1000 kHz but the capture is showing 714 kHz. Is this perhaps a limitation of the Reaper?

I have stepped through several reads & writes and confirmed that what is sent/received is what also appears in the LA. So, I’m feeling pretty good about the communications now. However, I’m not yet getting accurate temperatures back. I’m not ruling out bugs in the driver at this point or maybe a bad sensor.

@ ianlee74 - Try the other sensors; they can’t all be bad.

It has been a habit of mine to always add a pull up resistor on the MISO line for new designs.

That’s on the list but, unfortunately, I can’t get back to this until Sunday :frowning:

I’ll give that a try and see how things look.

I’d still love to be able to clean out that clock & MOSI bleed that’s in the MISO line. Clearly, I can’t do much about the Gadgeteer cable. Any suggestions for module-side improvements that might help eliminate it for the next board revision? I plan to add a ground plane to the top. Is it worth re-routing those lines so they don’t come close to each other on the board or do you think all the interference is from the cable? Any strategies for negating the interference? Maybe introducing more interference in the form of an inverted clock? Probably not worth the effort but I’m interested in learning all strategies.

You might try adding some series resistors like to the CLK, MOSI & MISO lines. Something like 220 ohm. If it does not help, you can always stick 0 ohm in there. But before you do that I would get one working rock solid first to see if there is still any ringing there. You might have tweaked the chip by running it without power this whole time. personally I would grab a module that I have never tried yet, add the jumper to power fix and then see how things go. I have ran things 2x longer than the standard Gadgeteer cable @ 5MHZ with no issues.

I’ve run things at 2.5 foot increments over 14 feet with little issue :whistle:

I doubt that a series resistor will help much, but it is easy enough to try. Note that once you started powering the chip, the signal only looks bad when the chip isn’t driving it (and the signal is not valid anyway). You could put a pull up there, and that will clean up the signal when it isn’t being driven. But it will make it harder for the chip to drive the line and this part is known for not having great drive strength, so put a very weak pull up on it. 50-100K would probably be better than 10K. It will probably make you feel better when you look at the signal with the Saleae, but it probably won’t improve the signal integrity.