I read the datasheet and what your are seeing is not by design. The part is supposed to put the next bit on the line at the first clock transition. It doesn’t say it, but one can infer that it should stay there, till the next bit is sent out.
I searched online and found people using it with an Arduino had issues with drive strength of the part. So here is what I would do.
First slow the communication down to 100KHz or so (you should have control of that in the SPI config of the master). Next, turn on the analog channel on MISO. Since your Saleae only supports 10MSa/s you need to slow the bus down to get a good time domain picture. Note that the Saleae is VERY slow when using analog and feels like it is dead when you ask it to take another capture. I just noticed a setting in Options --> Preferences --> Capture --> Enabled Upsampled Pipeline (which indicates it might be the reason it is so slow).
How long are your wires to the part?
It will be interesting to see the waveform of the MISO signal. I am guessing that it is not getting high enough,
That last image you posted doesn’t make sense in regards to the Saleae but the device might see it good. The MOSI is high when the clock is high, at least when you look at it but the Saleae sees it as a zero.
The device shows that the data is clocked in when the clock goes high with tDC being the time delay. For read, the data is presented after the falling edge of the clock with time tDCC and then your CPU will read when it sets the clock high. It seems that the read seems to be correct on MISO
It just seems to be an issue with the Saleae reading the MOSI side of things.
How does the device seem to be responding to the commands? Does it appear correct with regards to what appears on MOSI that you see on the Saleae as it is, ignoring the fact that it reads the value different?
The MOSI line (from the Reaper to the MAX part) is fine. The MISO line (from the MAX part to the Reaper) is not meeting the datasheet spec. The data sheet says that the data is clocked out on the rising edge of the clock, which means it should be high until the next rising edge of the clock (when it should change to the next bit). This means the Master is reading the value in the middle of the valid period, on the falling clock edge. The Saleae is showing that the line is high for only half the time it should be, which is why it is getting the wrong answer. My guess is that the Reaper might be reading it just before the falling edge of the clock and/or the MAX might be holding the value just beyond to clock edge. Zooming in on the trace would show it better.
Good point… Right now they are about 20cm because I have a 10cm cable from the mainboard to an Extender module where I have the Saleae tapped in and then another 10cm cable from the Extender to my module.
Lots of good ideas. I’ll do some more testing tonight. Thanks, guys!
Looking at all of Ian’s images, only the MOSI seems to be read wrong by the logic analyser but I assume that the bit pattern looks correct? MISO seems to be a duplicate of the MOSI value as the device should not be outputting anything on MISO until after the address byte (and needs bit 7 low for read and in Ian’s image it shows he is doing a write to register 0 following by the value 0x44) Atually, according to the datasheet, SDO (MISO) should be in the high impedance state (page 18) so the fact that the analyser reads anything is strange.
Ian, does the bit pattern shown by the logic analyser correspond with what the Repear sends, ignoring what the logic analyser reads the value as?
What is your SPI settings?
I recently had an issue with an LTC1867 ADC where I had the clock state wrong and the device was giving me data but I was seeing the same voltage input on 2 channels. Once I swapped the clock state it was good. It was causing a shift in the data bits.
Frogmore peeked my interest today in checking out the analog features of the Saleae that I hadn’t played with yet. So, I just turned that on and now something seems very apparent. Maybe I’m wrong, but it looks to me like there might be a problem with my board design and the clock is leaking over into the MISO line In the bottom graph you can see a zoom of the the last bit from the MISO LSB. Clearly, the lack of a flat top to the signal is causing the misreads.
So, now I think I’m at a point where I need some pro PCB design tips. There is a point (circled in red at the top of the board) where the MISO and SCK traces cross on different sides of the board. Could this be the problem? Is there a way to fix this short of a board rev? Actually, since the MISO trace is going to the extra header I can simply scratch it off with a knife and test… Do I maybe need to add a cap to the MISO line to clean it up in the next rev?
EDIT: I just tried scratching off the trace on the MISO line between the header and the via and it made no difference to the analog signal.
EDIT 2: I just realized that the MISO line is maxing out at about 1V and the MOSI at 3V…
Slow the SPI clock down, so there are more analog points. The filter is putting stuff there that isn’t really there. The analog sample rate and bandwidth is not good enough for that high speed of a clock.
Did you measure the DC resistance of the traces to check for shorts?
Did you check the solder connections?
Do you have a scope? If so set up a continuous communication and look at MISO line directly at the MAX chip.
This is one reason why many engineering boards have a lot of zero ohm resistors :wall:
Your signal is not parallel so should be OK. Your most likely place for this is the ribbon cable as the 2 lines are next to each other, pins 8 and 9 on the socket.
DO NOT put any caps on signal lines. You’ll degrade their edges.
One observation on your PCB design that I would make. The device is likely to have very little power draw but you should really use much thicker tracks on power rails. Also consider putting a ground plan on at least the top side, especially where you have analog parts. Not bad attempt though.
Do not put a cap on any of the signal lines, it would only make things worse. It sounds like you might have a solder whisker or partial board short. Try the dc measurement, MISO is right next to ground on the MAX chip. It would not be the first time this kind of thing has happened.
The previous images were taken at 100KHz. These are at 10KHz. From the scope it actually doesn’t look that bad. Should I not be concerned that the voltage level on the MISO line is so low? The measured source voltage at the module is 3.22V. Shouldn’t the signal be closer to that? Can the Reaper understand signals that low or do I need to add a level converter?
Thanks for the tips on the board. I have a long list of changes already for v1.1 if I can get close to proving that the thing even works.
I had planned to do a ground plane on this board but this was my first board using CircuitMaker and I couldn’t figure out how to do it and decided to just go without it this version. I hoped it was such a simple board it wouldn’t matter.
Can you open the MISO connection between the reaper and the MAX and measure the signal at the side of the MAX ?
Maybe the reapers portpin is doing something wrong…
So far, I’ve just had the device in a loop constantly reading the temperature and I’ve just been picking out a random sample until I can at least get something that seems “normal” from any regard. Then the plan was to send more specific data and verify against that. Once I get some of these more basic tests out of the way, I’ll do this. Since I also have a Maker Faire this weekend to prep for, I’ll probably be making slow progress the rest of this week.
That’s what I’m working on next. I’m going to eliminate the Extender module and connect the Saleae directly to the module. This will let me half the cable distance.
It does use the same terminology but I couldn’t quite figure it out. It doesn’t appear to work the same as the Eagle polygon fill. This seems to be one thing that was a lot easier in Eagle. With it I could just define the out boundary, tell it to pour, and it would automatically fill in around my traces and combine in the GND traces. It doesn’t appear to be that easy with CM/Altium. I could be wrong, though. I only spent an hour or so messing with it before I decided to “ship it!”.
[quote=“Lutz1”]Can you open the MISO connection between the reaper and the MAX and measure the signal at the side of the MAX ?
Maybe the reapers portpin is doing something wrong… [/quote]
Hmmm… I may have to break out my handy MakeWire module for that one. Let’s see what shortening the cable does first.
There’s no mention of a pull-up in the reference design. But, I guess it can’t hurt to see what happens.
Thanks for the continued feedback, guys! I’ll do another round of testing tonight. This has become a great learning experience.
There are allot of things to try for sure. Out of everything I have read here the one thing that sticks out like a sore thumb is the MISO levels. I would focus on that issue first more than anything else.
@ Ianlee I don’t know what you are measuring, but it is not what you think it is. The last picture you sent showed a waveform with a cycle time of ~1500ns, or 1.5us. I did the math and that does not match a frequency of 100KHz or 10KHz. I have attached a picture of a 1.5us cycle time square wave, as you can see the frequency is 650KHz.
The Saleae picture shows that CS looks right for the signal, so the clock frequency has not been set to why you think. However, that doesn’t explain the MISO line (MOSI is matching the clock, so probably okay). After thinking about this more it is likely that there is a very cold solder joint and you are picking up a lot of noise. A resistance measurement is a good way to check this, but the pressure of the probe might be enough to make the connection good for aw while.
Just for fun, I took a capture of a 2.6V 650KHz signal on one wire of a 200mm ribbon cable and another channel on the unconnected wire next in line. The yellow trace is almost 600mV and looks almost identical. The 1V you are seeing is high for something completely disconnected so I would expect there is some connection
So, you probably have something not connected on one end.
@ Dave your image matches shows sampling on the rising edge, which matches what the datasheet says, but it looks like you have the master set for the opposite. That is why the Saleae shows 1 for both of the first two bits in the first part but only for one for the second part on MOSI.
But MISO does not look like it matches what the spec says. The datasheet for the LTC1863 shows the transition between bits happening on the downward edge, which means the data should be high during the high part of SCK and also the low part. Now, if it is working for you, that is great, but I would guess it might not always do so.
SPI is a de facto standard so I guess whatever somebody implements is okay
It looks like the uploaded didn’t like that I unplugged and replugged my USB key, which is why the first image isn’t there. The second one has everything it did anyway.
In the bottom graph you can see a zoom of the the last bit from the MISO LSB. Clearly, the lack of a flat top to the signal is causing the misreads.
