SPI Modes on G400D


How do I select which mode I want to use for SPI communication? I looked at the SPI.Configuration Constructor but I only see the clk edge and clk idle.

How do i choose CPOL & CPHA?

Thank You,

@ dherrera - The SPI.Configuration method lets you select Clock_IdleState and Clock_Edge as parameters in the method call.

An example can be found here:

Hello PHITEK, thank you for the response.

From what I understand, CPOL is set by the Clock_Edge and that is the polarity at which the data is sampled, rising or falling edge of the clk.

Now, CPHA is the parameter used to shift the sampling phase, a false would indicate the data sampled on the leading clock edge, and a true indicating the data would be sampled on the trailing clk edge.

Clock_IdleState just sets whether the clock is high or low whenever data is not being sent. This isnt the same as the CPHA is it? Am i misunderstanding the two?

Thank You

@ dherrera - I would have to scope the signal to be sure.

This is quite typical when using the NETMF, one can get so far then hitting a limitation is a really possibility. I now prototype everything, seems to be the only way to be sure what is exactly implemented on each platform.

I will probably have a chance to try this is a few days when I get back to working on some SPI stepper motor controllers. I am just now working on a SPI slave in an FPGA design.

@ andre.m

From the link, CPHA shifts the phase of the clock.

In the SPI.Configuration method, Clock_IdleState parameter only allows you to set whether the clock will idle low or high but not the actual phase. Am i missing something?

@ dherrera - CPOL in the NETMF world is Clock_IdleState parameter, and CPHA is the ClockEdge parameter.
For the CPOL=0 set Clock_IdleState=false and for a CPHA=0 set the ClockEdge=true

SPI uses the rising edge or falling edges, not the polarity to indicate when the data bit is to be sampled. The polarity is more what level the clock signal is at when the bus is idle. So if the Clock_IdleState is false the clock starts from a “Low” state, and if the ClockEdge is false then clock must go “High” then on the falling edge transition back to a “Low” the data bit is sampled. However if the Clock_IdleState was true, then the first edge is a falling edge and data bit would be transferred sooner. This was measured on a G80 platform.

Hope this helps,

Good luck with your project.


Thank you for the clarification. I am having some issues with those two parameters. Whenever I run the following code, I see some problems with the SPI lines;

SPI.Configuration SPI_DDS = new SPI.Configuration(GHI.Pins.G400.PB18,  //Chip Select Port
                false, //ChipSelect Active State
                0,     //CLK Setup Time
                0,     //CLK Hold Time
                true, //Clock Idle State
                false, //Clcok Edge
                400,   //Clock Rate kHz
                SPI.SPI_module.SPI2); //SPI Module


ushort[] NOP = new ushort[] { 0x0000 };   // NOP instruction
ushort[] rx_data = new ushort[1];
ushort[] control = new ushort[] { 0x2100 };   // Control Register
ushort[] LSB = new ushort[] { 0x4F5C };       // Frequency Register LSB
ushort[] MSB = new ushort[] { 0x400A };       // Frequency Register MSB
ushort[] phase = new ushort[] { 0xC000 };     // Phase Register 
ushort[] exit = new ushort[] { 0x2000 };      // Exit Reset

MySPI.WriteRead(NOP, rx_data);

MySPI.WriteRead(control, rx_data);

MySPI.WriteRead(LSB, rx_data);

MySPI.WriteRead(MSB, rx_data);

MySPI.WriteRead(phase, rx_data);

MySPI.WriteRead(exit, rx_data);

I have attached two images.

scope_17.png shows the SPI lines with clk idle state = True and clk edge = False. As you can see, the lines never drop fully.

Now when I change clk idle state to False, the output waveforms seem better as shown in scope_16png

What can I do to fix this?

Thank You,

The Clock speed seems suspiciously low. I would try to start at 1000 and optimize from there.

@ dherrera - On the G400 the lowest clock frequency is about 510 kHz, looks like your are getting about 533 kHz, what are your SPI slave device specifications?
See reply #5 in this post.

The clock frequency I don’t believe is causing the change you are observing in signal levels. I would check the ground signal between the G400D and the SPI device and / or scope, is there any chance ground can be intermittently connecting?

By the way really like the scope you have.


I changed the clock frequency to 1MHz and am still getting the same problem. The only way that i get the clock and data lines to fully switch from high to low is by setting the clock idle state to false.
When the clock idle state is false, i get the correct signal that switches from high(3.3V) to low (0V) fully, same as o-scope screenshot from previous post.
When I set the clock idle state to true, thats when I see the clock and data lines not fully switch from high to low.

It seems that setting the clock idle state is messing something up on the G400. Any ideas how i can fix this?

There is a continuous ground plane on my board, and my SPI test points are close to the source with ground test points next to them.

@ dherrera - I’ll check what the signals look like on my G400 TH prototype this evening. I have two L6470 stepper motor controllers connected to the SPI bus. I am using the clock idle set to True.

The last time I ran these stepper motors was with 2015 R1, but I am now on 2016 R1 Pre-Release 1.

The only thing I can think of right now is to isolate the SPI bus from the slave device(s) to see if the signalling is been driven some how by the slaves or the G400.

Can you tell us a bit more about what the SPI slave device(s) are?

@ dherrera -

Because of somehow, the behavior of your slave device pull that pin to wrong state. Disconnect your slave device and measure these pin again you will see they are correct, no matter what idle or edge state are.

@ dherrera - I measured my SPI clock and it has an amplitude of about 3 Volts when idle and transitions to zero volts. About 13 uS to 7 uS before the SPI clock transitions low the clock signal seems to be floating to around 2 volts. The MOSI signal shows the same logic levels.

This is with no SPI devices connected.


So is result different without slave device conencted?

I measured my SPI clock and it has an amplitude of about 3 Volts when idle and transitions to zero volts[/quote]
How about if using external power?

About 13 uS to 7 uS before the SPI clock transitions low the clock signal seems to be floating to around 2 volts.[/quote]
Is it another issue? if so capture image for me please? Because all testing here seem be to fine.

@ Dat - I am just trying to help @ dherrera, what I am observing on my G400 looks fine to me. The SPI clock does seem to float (not a full 3.0 volts) but the SPI SS signal is not active so that should be fine.

Sorry for the confusion.


got it :smiley: