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SPI Interbyte delay


#1

Is there a way to perform multiple SPI Full duplex transactions with a predefined delay in the between each transaction? Let’s say I have to send 3 sets of 4 bytes and I want chip select toggled between each set of 4 for a duration of 10 micro seconds. Is this possible with TinyClr or am I doomed to write something in C.


#2

With our current API, that is not possible.


#3

Uh that’s very strange request for a SPI bus. Probably it is better to do 3 different transactions of 4 byte each in sequence … :thinking:

PS: Don’t tell me you are going to drive DAC85x2 Dacs from TI … :sob:


#4

Well the reason is that there is a long delay between when one transaction get’s sent out and the next. This is because of the latencies involved with the managed framework. I was wondering if it was possible to stay in the low level code until all bytes were sent, by implementing a delay between each transaction.

Nah, I’m driving L6480s