Parallel IO using register class
I was experimenting with using the Register class to implement a parallel I/O port.
Chose the FEZ MINI because it has 13 contiguous bits (P0.16 – P0.28) brought out to the headers.
I attached a picture of the timing waveform from my logic analyzer and the code file.
NOTE: The first 2 lines in the Main (disabling the SPI?) were not in the original test…something I added this morning and plan to try out this evening.
The signals (top-to-bottom) are:
D0-Data Bit 0-P0.16
D1-Data Bit 1-MISO0 (never changes)
D2-Data Bit 2-MOSI0 (never changes)
D3-Data Bit 3-SD_CLK
D4-Data Bit 4-SD_CMD
D5-Data Bit 5-SD_PEN
D6-Data Bit 6-SD_DAT0
D7-Data Bit 7-ADC0
You’ll notice D1 and D2 don’t change…these are MISO0 and MOSI0 pins…which is my dilemma…all other signals are ‘as expected’
According to my logic analyzer, the time between CS rise (8 writes) is around 2.15ms so that should result in 3720 single byte writes per second ((1/0.00215)*8)…writing to a 40x24 character display would take around 0.25 seconds(?)
My initial question:
Will clearing the PCSPI bit of the PCONP register disable the SPI and thus cause my D1 and D2 signals to output?
For register location and description, see LPC23xx User Manual