Could anyone explain why as I thought this was a bit of a fake SPI interface and by using the chip select line you could signal the chip being used and hence could share some pins (maybe the chip select pin isn’t shared, but the other pins should be??)
yeah, with SPI you can’t share CS pin - by definition you don’t want to select two chips at the same time to communicate to.
Technically, the other pins in an SPI port could be shared. But the GHI driver you show is NOT using an SPI port, it’s using an X/Y socket. So it makes no sense to declare them as shared.
@ Brett - So it if was using SPI then I would mark pin 3 (the chip select) as not being shareable and everything else would be shareable.
I was thinking of the case (that I test) where I have multiple max31855 chips connected but I can’t assume that is all I have connected on X/Y sockets as that could cause problems for other modules (ie that weren’t max31855 chips), so I’ll mark the 3 pins as share=false.
The question I have with multi-module setups is what do you cater for - multiple MAX3xxxx chips on a single “module” all using the same pins? If so, that really is only one mega-module, that happens to have say 3x CS pins and some standard IO pins. If you’re wanting the possibility to connect 3x of your current “module” on different sockets, then shared=false will still work in that scenario.