I am using the FEZ Hydra and FEZ Cobra II with an analog to digital converter. The ADC outputs data on falling clock edges and has an access time of ~ 60ns.
When using the Hydra board the data coming from the ADC is correct. However, when using the Cobra Board the data coming in is incorrect. The difference between the Hydra and Cobra bits occurs when the data output falls from 0-1 or rises from 1-0. Since the clock falling edge lines up almost exactly with when the data is being output I believe the Cobra board does not give enough time to the SPI read operation before reading in the value in the MISO pin so the data is not able to update. I believe this makes sense since the Hydra uses a slower processor and may therefore leave enough time for the MISO pin to show the correct output from the ADC.
I was wondering if there was a way to delay the SPI read operation by a certain nanoseconds after the clock falling edge.
Yes, though SPI.configuration allows me to control the chip select hold times and the clock pulse widths it does not allow me control over the SPI Read operation.
I would like to initiate the SPI READ operation about 100 nanoseconds after every SPI CLOCK falling edge. That is, I want the MISO line to read in 100 nanoseconds after the falling edge of the clock is sent. Is there any way to do this?
The datasheet for the AD7321 says it works with a clock up to 10Mhz and the clock I set using SPI config is 1000Khz = 1Mhz. I can not control the output of the ADC because it simply sends it when there is a falling edge in SCLK, this is why I am trying to delay the read.
The Hydra board does have sufficent delay and reads the output correctly however, with the Cobra it reads the MISO line before the output has had a chance to be updated and sent from the ADC dataout line.
I have tried changing the clock edge, though this may solve the read in problem since I reading in at the delay rising edge, it creates the additional problem that it will write bits out at the rising clock edge as well however, the ADC samples the bits at the MOSI line at the falling edge so now the control register of the ADC is set incorrectly.
Update: I am now going to try starting clock idle low and sampling data on rising edges I think this may work.
Nvm, it didn’t quite work because now the SPI was outputting data on falling clock edges and hence the control register was being incorrectly set since the ADC also reads in data on falling edges.