RLPLite - Cerberus - R/O Base and R/W Base (Clarification needed)

I was following this old thread :


but am still a little confused…

There are 2 tabs in the option in uVision.

which has:
“Read/Only memory Areas”, which has IROM1 ticked and set to 0x0 for Start and 0x80000 for size.
and “Read/Write memory Areas” which has IRAM1 ticked and set to 0x20000000 and 0x20000 for size.

has R/O base set to: 0x00000000
and R/W base set o: 0x20000000

I am confused for Cerberus which values to I change? Assuming I am using the non-ethernet board (Fez Cerb 40 II)

The post says:
“For the Non Ethernet firmware, the region is 8KB (0x2000) and begins at address 0x20000000.”

but which fields do I set?

It’s probably confusing but the key statement in the documentation is [quote]You may split these address spaces as you wish[/quote]

The split into R/O and R/W is fairly arbitrary. By default most linkers place all function code into sections marked R/O. Modifiable storage goes into R/W sections. So, in the documentation, the example using the FEZ Hydra reserves 0x80000 for all the machine code, and the rest of the total RAM is available for variable storage (R/W starting at 0xA0080000). You can look at the map file to make adjustments to your initial section size divisions.

Thanks for the reply Jeff :slight_smile:

I think it makes sense now. So just to clarify, do you mean:

On the non Ethernet Cerberus I have 8k I can split up as I like between Readonly (ROM) and writable memory (RAM).
Start address: 0x20000000
Size: 0x2000

So for the Cerberus, if I wanted 4k for rom and 4k for ram
On the “Target” tab of the Target options, I’d set:

IROM1: addr: 0x20000000 size: 0x1000
IRAM1: addr: 0x20001000 size: 0x1000

and on the linker page:

R/O base: 0x20000000
R/W base: 0x20001000


When I was playing with Keil, I never touched those…

Ive got it working and like Simon said, i didnt need to the those settings.
Thanks for the help everyone :slight_smile: