I never did find a published way to determine Pclk, but I sort of backed into it by running the equation backwards from known results/configuration.
This link is quite helpful in setting up the register values: http://prototalk.net/forums/showthread.php?t=11
Not so clear in all this mess is the fact that you have to write DLAB to 1, then write DLM and DLL, [italic]then write DLAB back to 0[/italic]. Officially the Fractional Divide Register will not have any effect if DLMx256+DLL is below 3. What I found is that any value below 3 had no effect, regardless of the status of FDR.
According to my oscilloscope the fastest bit rate I can get out of my Panda-II is ~512kHz. Interestingly, my AX12’s are responding to that frequency even though they’re programmed for 1MHz, and work my AVR that is talking at 1MHz (verified with the scope). I was not aware that the AX12 had any kind of auto baud detection, but I can’t explain it any other way.
FDR = 0x10
DLM = 0x00
DLL = 0x03 (can’t seem to go any lower)
Based on the values above, and what I see in PCLK_UART2, the UART is maxed out at 512. What am I missing? Are some of the UARTS faster than others? I’m using UART2 (COM3).