I’m very happy to announce a new shield for the NETMF/*duino community: the ÜberShield. In short, this is a shield with a Xilinx FPGA, clock oscillator, and 64 available dedicated I/O. Further details are available at http://ubershield.com. At present, the board is shipping with a combination GPIO/PWM core. All 64 of the dedicated header digital pins are available for either input or output, and 32 of them are also able to generate PWM signals. The PWM engine has 32 bit/1us resolution, meaning your pulse width and period can range from 2us to just over one hour, in 1us steps. In addition, all 32 PWM channels are time-aligned, and there’s a master “terminate” count, so you can create complex waveforms like stepper motor control sequences. Further discussion and some examples are in the ÜberShield forums (http://forums.ubershield.com). A full NETMF library is available to support the GPIO and PWM functionality.
In addition, should you want to write your own core in Verilog/VHDL or using Xilinx’s schematic capture tool, a bitstream loader is available for the FEZ Panda and Domino platforms. This loader allows you to transfer your design into the FPGA without using a specialized JTAG cable. It can also be used to upgrade the shield’s functionality as new cores are released by the community.