This is more directed towards the GHI team. 
I have an RLP servo driver that can drive up to 48 servos at this time, 12 servos per 2.5ms window. More servos can be driven if the buffers are expanded.
It depends heavily on interrupts firing when they should which all works very nicely. It also uses an RLP task to respawn the servo code every 2.5ms.
The problem comes in when the managed application uses the onewire lib to read from a sensor. Suddenly all my interupts gets delayed by 0.2ms or more which really puts a kink in things as it makes all the servos jump.
Is there any way around this? I know that the timing is “critical” around reading/writing a bit, but between bits it isn’t critical. Are interrupts disabled for the whole byte or only during critical times?
To run one wire in software, interrupts must be disabled. I am not sure what is the best way around this
That is what I assumed. But…
As far as I know, to read a bit the wire is pulled low for 5us, then read after 30us. This is critcal and ISRs must be disabled, but after that timing isn’t an issue and ISRs can be handled.
The timing critical part starts with the falling edge of the wire and ends 30us later. The next timing critical part starts at the next falling edge.
Can ISRs not be handles between bits?
This maybe enhanced in future like you are explaining.
A temporarily option is to implement your own one wire lbs that doesn’t disable interrupts for long time.
Will look into that.
Is there anything else that disables interrupts?
Ok, let me rephrase.
Is there anything else that disables the ISRs for more than a few micro seconds?
I’m trying to put together a commercial robot kit, and I need to know whether I must scrap it or not… 
We do not use the fast IRQ vector. Maybe it can be used I am not sure.
Yes there are drivers everywhere that disable interrupt but you can tell once you used the drivers. Your robot will use some specific drivers I assume?
How do you disable interrupts? The only way I can see is to back up the VICIntEnable register and to clear it. Then to restore it when required. If this is the case then the FIQ is disabled along with the IRQs.
On 1-wire. I think that IRQs must only be disabled during the first 5us while writing a “1” or reading a bit. Writing a “0” doesn’t need to disable IRQs at all…
Busy writing RLP 1-wire lib. Then I can try to add high speed too…
