Identifying Pins on the Hydra

[ChrisO]

Hi Everyone,

I know his may be a stupid question, but, GPIO Pins on the FEZ Hydra?

(Cpu.Pin)FEZ_Pin.Digital...   <--

The following seems to be the most appropriate:

(Cpu.Pin)GHI.Hardware.FEZHydra.Pin.PD16 <--

I am having trouble with the Schematic and viewing the Pins as they are laid out. GPIO_Pin1 for example does not show:

Cpu.Pin.GPIO_Pin1 <--

The Schematic: http://www.ghielectronics.com/downloads/schematic/FEZ_Hydra_Mainboard_SCH.pdf

What am I missing? Please someone point out where I am going wrong.

All the Best

Chris

[taylorza]

@ ChrisO - GPIO_Pin1 will map to pin PA1 which is on socket 8 pin 6.

The GPIO pin numbers are a NETMF abstraction of the physical pins. The processor has blocks of 32 pins, the first is the PA block, which has pins PA0 - PA31 and corresponds to pins 0-31, the second block is the PB block which has pins PB0 - PB31 which correspond to pins 32-63 and so on.

[ChrisO]

@ taylorza - you’re a champion thanks +1 from me!

[Brett]

My suggestion - always use the PAx PBx PCx PDx pin enumerations, they are clearly documented on the schematic so make the most sense from a “physical” perspective. The enumerations Cpu.Pin.GPIO_Pin1 are least relevant in my view, as they just map back to a framework mapping not a physical one (sure, GPIO_Pin1 == PA1, but you have to dig deep into the framework code to actually confirm that).

[ChrisO]

Thanks Brett! +1 for your advice!

@Brett

My suggestion - always use the PAx PBx PCx PDx pin enumerations, they are clearly documented on the schematic so make the most sense from a “physical” perspective. The enumerations Cpu.Pin.GPIO_Pin1 are least relevant in my view, as they just map back to a framework mapping not a physical one (sure, GPIO_Pin1 == PA1, but you have to dig deep into the framework code to actually confirm that).