Hydra board revisions and EMC

I have been working with the Hydra board for over a year now, and in that time I have seen 3 different revisions each time we buy. I started with 1.2, then I got 1.2b, and now I have heard direct from GHI that there is a 1.3 version. The problem is that the new schematics and layout are not available on the website, and the designs are different. Rev 1.2b has at least 1 additional cap, C6, shown in the picture below. And I was told 1.3 has another ground layer.

Has anyone else noticed this? Have you received any sort of update from GHI saying that the design has changed? Does anyone have the 1.2b or 1.3 schematic, BOM, and layout?

We found this only because we tried to test our system that uses the Hydra for FCC Class A EMC compliance, and it failed. There is a 100MHz clock signal coming off the Hydra leaking all over the system. It originates between the MCU (IC5) and the memory (IC4). There is a capacitor, C6, on this line but it’s not in the schematic or layout.

Any advice would be greatly appreciated.

@ LukeG - as mentioned in emails, hydra is an open source reference design made in eagle for those wishing to get into porting netmf. It is not FCC CE tested like our SoM for example.

Also, improvements are made on hydra without notifications but this is not the case in SoMs, which are meant for volume production use.

As far as noise, the community will tell you this is something we all noticed when tried using gps with hydra. As a reference open design, we were not concerned but in 1.3 we shielded the board to reduce noise, still no fcc.

Hydra sells at near cost as a contribution to the open community. It is a simple 4 layer design, no fcc and no guarantees. We will check and improve the product description as necessary.

You can try 1.3 to see if it is better for you. We also provide all the design files so you can make any necessary changes. We will happily provide the individual reference designs.

We are available to provide everything we have for free and we are also available for consultation work as well. Just let us know how we can assist you please.

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I’m still waiting on those schematic and layout from you guys for Rev 1.2b. I thought I would reach out to the community to see if anyone else noticed you guys were changing the designs without updating your information. Or if GHI had provided that data for their “open source” platform.

I don’t think it’s too much to ask to be provided with an updated schematic and layout for what we purchased after purchasing over 50 boards. And we have another order for 75 boards pending.

Finally received. Thank you.

Please let us know if you need anything else. And if you have suggested improvement for the noise and like to share, we would love to incorporate in the next version.

We are working the issue now. We know the 100MHz SDCK to the memory is the culprit. It leaks onto the data bus. We have not figured out how it leaks onto our board yet though. Could be conducted, could be radiated. I will update with progress.

You need to try the 1.3. I think it will be a lot better. Shoot me an email with your address if interested.

So the EMC failure is caused by the clock signal, SDCK, from the MCU (IC5 pin U8) to the SDRAM (IC4 pin 38). This signal is a 100MHz sine wave, and the measurement on a scope is attached. We found the signal is extremely high, almost 7Vpk-pk. This signal leaks onto the data bus of the memory, and elsewhere in our system. We have not found the exact leakage path yet, but it could be due to poor grounding on the 1.2b board.

We have found that by increasing C6 (a 20pF shunt cap on SDCK) from 20pF to 56pF drops the level from 7Vpk-pk to 5.8Vpk-pk, but then the Hydra will not boot up. I suspect that this is due to the slew rate beign reduced on the clock signal as the K4S561632A datasheet specifies the clock is “active on the positive going edge to sample all inputs.”

I have also attached a picture of the SPI clock (IC5 pin C11). This is a relatively lean square wave at 3MHz. It does have a high ringing, so the peak to peak is still high at almost 6V, but the transitions are clean.

We are at a loss here because there is nothing we can change within the part to reduce the level of the 100MHz clock signal or make it more square wave.

Are you measuring that with a high-frequency probe? I suspect a lot of the shape you see is a measurement artifact. Remember a normal scope probe is about 10pf.

Can I ask how you know the emc issue is this 100MHz signal? And how you then know it’s leaking onto the data bus?

The probe is a 500MHz probe with 10pF.

So in our design, we take the Hydra board and plug it into a motherboard. When you button up the whole chassis (solid ground surrounding everything), we see harmonics of this signal leaking out of the LCD display and the Ethernet ports.

If you disconnect the LCD only, no change.
If you disconnect the Ethernet cables, no change.
If you disconnect both LCD and Ethernet ports there is a significant change.
If you remove the Hydra the signal disappears completely. If you measure the Hydra by itself, the signals are there.

The Hydra is not used as our communication processor. There are 2 other IC’s between the Hydra and the Ethernet ports.

We measured the data bus, and you can see the 100MHz noise on it.

If that is really a 100MHz sine wave it won’t have any harmonics.

Is 500MHz is a measure of your scope sample rate not the probe. An high freq probe is normally an expensive active device. You could make a h-field probe to try and sniff out the source of the emmission. This is just a bit of coax with a small loop with a few turns on the end and a bnc connector on the other.

I presume you’ve checked the power supply lines. The standard 100pf decoupling caps don’t do much above 100mhz. You could add some smaller caps in parallel (2pf 0603 would be ideal).

This guide has an example of a h-field probe construction. You don’t need to use semi rigid if you don’t want.


You are right. There should not be any harmonics of a pure sine wave, but I doubt it is that perfect. 500MHz is the scope probe and the scope is rated for 500MHz as well. But even if it was filtering out higher harmonics, I think we should see some sort of square shape. Not a pure sine wave.

See attached for the measured results at an EMC lab, inside an anechoic chamber with an H probe antenna at 3m away.

Yuk, that is nasty. Maybe the 100mhz is being modulated by the other clocks or data lines.

Have you tried copper tape and ferrites?

yes and yes. Forgot to add this in the last post. Every IC on the motherboard has a ferrite bead and decoupling caps of 100nF and some also have 4.7uF and 22uF. Where the hydra gets 3.3V fromt he motherboard, there is a ferrite bead and 22uF, 4.7uF, and 100nF decoupling caps.

We tried adding a layer of copper tape to the top side of the board (away from the motherboard) because we thought it might just be poor grounding. However, there was no effect. There is not much room to put a shield between the motherboard and Hydra.

See pics. Pointer finger for scale reference on the space between boards. The last is without a Hydra mounted.

cool board… :slight_smile: I wonder what it’ll do?

I am curious too.

Remote RF power monitor and control unit for distributed antenna systems.

Looks ok to me. I guess you don’t want to respin that motherboard.

You could make a carrier board for a G120 or G400 to fit the same footprint as the hydra. Add a board level shield (laird do some nice off the shelf ones) and some in-line filter passives(something like these are good http://www.digikey.co.uk/product-detail/en/NFA21SL307X1A48L/NFA21SL307X1A48L-ND/4359715 ) on all IO lines going in and out to be sure.

Hopefully the 1.3 version of the hyrda board will be better. That’s your quick fix.

The latest 4.3.4 firmware reduced the emi interference from my G120. It has a lower power idle state that makes a big difference. Not much use on the hydra though.

I’m teaching you to suck eggs. The problem is that the hydra already comes with its own distributed antenna.