I once read on somewhere on these forums (or perhaps by email) that the EMX 8 layer pcb was difficult to design. Does anyknow know the answers to the following questions anout the EMX?
- What was the reason for an 8 layer design? Complexity, Cost, Size or Other. I’ve always figured it was size.
- What kind of PCB Lamination was used? Standard, Hybryd or Fusion (I assumed it was not Hybryd)
- How is are the blind VIAs plated? Is it the same as the through hole ones?
Those are not kind of info we usually share but I can tell you there is no blind vias.
I understand about the info part, I know its not something that is part of your IP, I’m trying to learn from your examples.
Could you then share the type of Lamination? Was it Standard or Hybryd?
Hydra is a great example to learn from as it is all open. It has BGA and SDRAM which is a challenge to most designers.
Yea but the Hydra isn’t an 8 layer board?
The number of layers are generally related the number of signals to route, and the number of power planes required. If I had to guess then there are 4 power planes with different voltages and 4 signal layers for example 3.3V, 2.5V, 1.8V, GND.
The 4 signal layers are requierd because the layers become full or because there are too many “crossing” signals. Once you design a complex 2 layer board you will start to yern for more layers to do the routing on.
Blind vias are really expensive because the board gets assembled in stages. Yes they mus tbe plated. Thus the board must be assembled from the inside out, plating the vias at every stage, layer by layer.
Hum… do you have any info on how vias a plated?
They start with a double sided board. They first drill all the holes that must be plated. This is before etching. Then they coat the holes with a conductive paint, or such, then they electro plate the whole PCB. This lays down copper in the vias but also on the outside layers.(this is why, on a multi layer board without burried vias, the inner layers are 1oz and the outer layers are 2oz, because of the extra copper plating to form the vias)
Then they etch the board.
If it is a two layer then they add the solter mask etc.
If it is a multi layer, with blind vias, then they laminate another singlesided board onto each side. Then they drill move vias, paint, plate. The previously drilled/plated vias are now burried inside the board.
But how do they get the vias to pass through the sheet of prepreg?
They drill a hole through, then form the via in the hole.
hum… so they just drill the holes after they bond and then plate. since the copper layers inside are protected they won’t plate also. Any layers that are exposed at the site of the drill will also be plated therefore you just have to pull back all the internal layers from that particular hole. Interesting. How did you come to learn this Errol?
I suspect that there is a pad on every layer, whether you connect to that via on that layer or not. Thus you are “forced” to pull back from the via on all layers…
Studied PCB making a few years ago. Wanted to make through hole plating at home. Gave up…
You should try again. I’m going to try making 2 layers with via’s this year. There are videos on youtube that I found that describe how to do it. Plus silk screening.
Naa, going to DorkbotPDX is just SO much simpler. And they can do lines finer than I can do at home. And most(all?) boards are gold plated. Can’t beat that…
I did “through holes” for my CANxtra keypad. Think I placed all the details on the wiki. But I just used conductive Silver varnish for the through holes. There isn’t much current so I could get away with that…
and if you don’t need them to be blind or “neat” like for the capacitive touch keypad needed, you can just use the old “solder in a chunk of wire” technique, works wonders as long as you have large enough holes (or small enough wire )
Used that method for the last 15 years. A few years ago I got some 0.2mm drills from a engineering shop. Had to use single strands from multi stranded wire to make the vias.
It works OK, but you can’t place a via under a SMD chip. That is a big problem, and takes a lot of extra design work and PCB space to work around that issue…