FEz product power consumption : Help me!


My project is quite simple…

I have to embed into a satelite an electronic card.

I don’t need a high frequency (72 could be fine) but my requirement are “quite” tight
concerning the consumption of the card.

In terms of IO, the cerb40 looks perfect for me… the software will read values coming from
IO, SPI, Uart… but none of the “components” connected to the card will get their power
from the card.

So my question is quite simple : Taking into account the fact that I want (expect) less or equal than 40 mA in normal working phase, do you think cerb40 will reach that level ?

If not, are there any “Micro framework” cards that could challenge these values of 40 mA power consumption in normal mode ?

Thanks for your advices.

You should be fine if you only need one but why not add a transistor then you do not need to worry about this?

I don’t understand your sentence :

“You should be fine if you only need one”… need one what ?

when running the Cerb40, what power consumption do I have if I don’t provide power
to any devices connected to the card ?

If power consumption is critical you may want to consider a reduced clock speed and or sleeping with a periodic wakeup to check data if your application can handle it.

I’m not familiar with the Cerb40 power consumption spec, but it should be easy to measure.

Measuring ain’t a problem but I don’t own any cerb40…

that’s why I’m asking the question.

Is there anyone at GHI who could tell me what is the consumption of the Cerb40 in normal mode or in idle mode ?

I’m sure someone can provide an answer with values…


I can’t afford to have more than 40 mA so, if none of the GHI products can provide this,
I will sadly have to look somewhere else and I really want to work with Micro framework and if possible ghi products…

If you look at the STM data sheet :

230 μA/MHz at 168 MHz running Coremark benchmark from Flash memory (peripherals off)

Thats 38.640 mA (peripherals off) this means you have to start clocking down to start…

yep, thanks

I could downclocking the cerb40 to work at 20 MHz and then reduce power consumption.

Are they any drawbacks in doing such a downclocking ?

Depending on what clock you are downclocking you will have to get timing back in order for all the functionalytie you want to use.

from the datasheet:
The timers connected to APB2 are clocked from TIMxCLK up to 168 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 84 MHz or 168 MHz, depending on TIMPRE bit configuration in the RCC_DCKCFGR register

So if you clock down APB2 then all ADC, SPI1 etc etc need to get some bit poking in the devide registers to come back to the correct speed.

It is possible to downclock a Cerb40 with no hardware change. The external quartz is 12MHz and there is an internal PLL to make a faster internal clock.
All the settings are in the solution platform.h.
You need to recompile the firmware to change this.

The Cerb40 need only 3.3V, if you have 40mA on 5V, this can be more available on 3.3V

Ypu also have to consider the duty cycle.

Ok thanks NicolasG

I will have to find how to compile firmware… I guess there might be some tutorials
or explanations to achieve such an action.

There are some resources here to recompile the firmware but you have to think about the real need.
If your task need to be awake most of the time, it’s ok to downclock.
If you’re sleeping 90% of the time, is it really necessary to do the task two times slowlier and sleep only 80%?

I think maybe the solution could be down clocking during the idle period?
I know GHI has suggested over clocking just during a intensive task and then switch back…
Doing the opposite should also work just fine and this is just 2 pokes…

[EDIT] like here for the G120 :

@ The Monz

In my earlier post to you I suggested hibernating with periodic wake up because as is now being discussed it effective for reducing average power consumption without downclocking. I use the technique in an application that wakes up from hibernation every second to collect some data effectively reducing average current draw proportional to the awake and hibernate time ratios and current draws.

Unless you have a peak current draw issue this may get you below 40ma without downclocking. All depends on how long you want to be awake and what you need to do.

I don’t think downclocking during hibernate will buy much because it’s already in low power mode. Here’s a link to an old post that talks some power saving steps on a Panda II - I know you are looking at a Cerb40, but the ideas are similar.


thanks a lot guys

You’re right… downclocking may no be THE solution… but going asleep might be…

To “explain” the situation with more details, the cerb40 will be embedded in a satelite so, the power consumption due to battery life is tremendously important.

I am not in charge of the electronic parts but as I know GHI product, in a way, I’m in charge of “validating” the selection of the Cerb40… Being the computer of the project, I do whatever I can to switch to Microframework solution as long as it fit our needs in terms of power saving.

I really appreciated your help guys… I’ll go back for more questions…