I’m testing FEZ Cerb40 II low power modes using the latest SDK available (4.3 (QFE1)).
Using the example code in the documentation (and an Output pin to see an heart beat) I’m reading 5mA when calling
PowerState.Sleep(SleepLevel.DeepSleep, HardwareEvent.OEMReserved2)
It seems a lot for a sleeping processor waiting to wakeup from RTC…
I would like to play around with the registers trying to power down unused modules and those sorts of tweaking but, as I don’t know what is going on behind the scenes with NETMF, I was wondering if you guys could give some hints on what’s happening on power down/power up. Also appreciate if you let me know if there is any particular register I shouldn’t touch so I don’t brick my FEZ.
That seems a bit higher than the current Justin measured on his mountaineer firmwared stm32 chip.
I looked up the voltage regulator part from the schematic (lm1117mp-3.3). Looks like it has a typical minimum current of 1.7mA and max min current of 5mA. It could be that you have either a worse case regulator of there is something about the way it’s set up.
The regs I’m using on my boards are way better than this one. I bet there are some form factor compatiable chips availiable so you could desolder it and stick a better one in.
@ JSimoes - I wonder what the effect is of dropping the supply voltage down to say 2v. I think this chip runs from 1.8+. Can you do a test now you have bypassed the LDO?
Now this brings a suggestion for a new board: a FEZ Cerb40 III, or FEZ stamp or FEZ mini, or whatever you want to call it with just the CPU, crystals and the absolute minimum BOM. We can take care of the LDO, USB connector and other stuff.
@ ianlee74 - :think: just looked for that name on the catalog to refresh my mind. The original FEZ Cerb40 is about the same size as the new version. It wasn’t exactly that what I had in mind… rather a smaller form factor. Just the absolute minimum BOM.
@ Gus - In order to be able to make a smaller device (the one were it will fit into).
You guys can do a pretty good job on squeezing in stuff! With castellation termination instead of a DIP would save a lot of board space.
Just a quick comparison.
Yes that is exactly what I’m comparing: two different PCB technologies.
The goal here is to have the smallest possible form factor. Using surface mount sure helps reaching that goal.
I understand that DIP format is great for hobby and prototyping but this would be for a SoM module, fit for production.
I believe this would be a nice addition for GHI catalogue. You already have the G120, that is a great module. But it’s missing an alternative for projects where the required resources aren’t a lot of memory and graphical interfaces but instead simple IO, possibly networking and a couple of the usual SPI/I2C/CAN/ADC/1Wire.