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Code for tech talks


#1

There is a new repo now for all code examples used in tech talks. https://github.com/ghi-electronics/Tech-Talks

Feedback is welcome.


#2

Cool!
Should each example have a link back to the talk, just in case someone comes across it via GIT only

e.g. Link for Bit-Banging: Part 2 - Tech Talk - #028


#3

After we upload all, yes.


#4

Oh and by the way did anyone find the solution for Driving the Circular 2 chip cascaded controller?
I dont have one to play with, the manufacture doesnt have much about it on their web site.
Looking at the SEED schematic, it first look like data and clk is common to all chips, which made me think there must be a ‘command’ to ID the chips/bank, but that would require a way to first ID the chips (HW or WS method).

BUT looking at the schematic of the chip, I can see what it might be. Data out of the first chip is not just linked to DI.
Its actually the output of the 208 bit shift register, So I imagine for multiple cascaded ships you would just need to write two joined (data & command)'s into the 'first chip (assume 416 bits worth) and it would basically ‘falls through’ the first shift register and load the 2nd shift register. And by the time you have written 416 bits both registers have the data you wanted , then you latch it, into the latch and the two chips should have different data.

Its actually quiet a simple but smart way to do it for the intended application of driving a LED wall display, as just with the two pins D & CLK you can push all the data for 100’s of LED drivers/chips serially in one batch and not have to worry about any control/chip enable lines which would be very messy to handle.


#5

Still not working


#6

hmm odd…
Interesting to put a CRO on the DIn of the 2nd chip and see if data is actually getting through?

Tried a longer TSTOP? I think due to propergation delays if high l# of chips, but worth a shot…

  • Tstop (min.) for cascade application must > “200ns + N*10ns” (N is the cascade number of drivers)

MY9221 transmits data from the DI pin on both rising and falling edge of the data
clock (DCKI). After whole given serial data are shifted into 208-bit shift register, then the
data can be loaded into the latch register by internal-latch function. The serial data will be
shifted out from the DO pin on the synchronization of the rising and falling edge of DCKI.

How about the trying different Output waveform (Bit 4 in CMD)?

CMD[4] sep Output waveform select
0 : MY-PWM output waveform (similar to traditional waveform)
1 : APDM output waveform