The chip spec lists the stm32f as having 2x CAN controllers and 3x SPI, but the pinouts on the Cerb40 only list 1 CAN port and 1 SPI port.
Are any of the other pins tied to the other CAN controllers and SPI ports?
Everything is multiplexed on microcontrollers, please check datasheet and schematics to determine where the pins are.
According to the datasheet, table 7, the pins line up like this:
[quote]
SPI1_NSS PA4, PA15
SPI1_SCK PA5, PB3
SPI1_MISO PA6, PB4
SPI1_MOSI PA7, PB5
SPI2_NSS PB9, PB12, PI0
SPI2_SCK PB10, PB13, PI1
SPI2_MISO PB14, PC2, PI2
SPI2_MOSI PB15, PC3, PI3
SPI3_NSS PA4, PA15
SPI3_SCK PB3, PC10
SPI3_MISO PB4, PC11
SPI3_MOSI PB5, PC12[/quote]
Now, the Oberon firmware is less flexible than the hardware, it maps up the pins like this:
[quote]
SPI1_SCLK PA5
SPI1_MISO PA6
SPI1_MOSI PA7
SPI2_SCLK PB13
SPI2_MISO PB14
SPI2_MOSI PB15
SPI3_SCLK PB3
SPI3_MISO PB4
SPI3_MOSI PB5[/quote]
The Cerb40 doesn’t have PB13 exposed, so SPI2 is out using the current firmware. Given the hardware’s capabilities, however, it would be possible to set it up like this and use all three SPI modules:
PA5 -> SPI1_SCK
PA6 -> SPI1_MISO
PA7 -> SPI1_MOSI
PB10 -> SPI2_SCK
PB11 -> SPI2_MISO
PB14 -> SPI2_MOSI
PC10 -> SPI3_SCK
PC11 -> SPI3_MISO
PC12 -> SPI3_MOSI
As an aside, the NETMF seems to be under the assumption that this sort of pin mapping isn’t possible. It certainly doesn’t have the configuration options to remap pins like this. The STM32 is a much more capable device than the NETMF accounts for, and so a LOT of its capabilities go unused (or require some other way to set up, like these alternate pin mappings).
This is something that could be contributed by the community.
Thanks for looking into this. It seems like a quite a bit of work before this offering is capable of being used to its full potential.
If ever. Like I said, the NETMF was built on the assumption that a certain SPI “module” was mapped to a certain set of pins, for example. This was true of older hardware, and lots of newer hardware, as well… I believe that NXP’s current line of Cortex-M MCUs, such as the LPC17xx, still have this sort of limitation.
It would take a lot of core NETMF work to resolve this limitation.
Based on the limitations above and the current pinout on the cerb40, it does not seem possible to have 2x can and even 1 SPI.
So its either 1x CAN and 1x SPI or 2x CAN and no SPI 
You can’t have it all…
The hardware is perfectly capable of doing 2x CAN and 3x SPI, at least in the larger packages. In the 64-pin part in Cerberus, you could do 2x CAN and 2x SPI.
The Oberon firmware doesn’t have CAN implemented, it doesn’t seem.