We have a custom board that uses the G120 SOM.
We call the board in an enclosure with cell modem, battery back-up…a PAC
We are working on the next gen that will use one of the following:
BTW: the page: https://www.ghielectronics.com/sitcore/som/ is (initially) confusing.
It shows pics at the top going from left to right as:
Comparison grid shows SOMs going from left to right:
Visually, takes more than a glance to figure out which SOM pic goes with which Comparison grid spec column.
Anyway, we have many PACs deployed in the field.
The PAC is remotely commanded and controlled…IOT
IO let’s us know the status of the PAC and any attached equipment.
IO consists of digital and analog.
A primary status indicator of attached equipment is brought in via A4 / P1_30
We use A0 - A7 for status indication, along with several digitals.
We have seen and known for quite some time that analog values can freeze (not change value when pin voltage changes) and also show value = 0 event though there may be 3.3v applied to the pin(s).
Our workaround is to use a known value.
We use the incoming power to the PAC (24VDC to 480VAC) to signal if analogs are frozen.
If analogs were frozen the PAC would power-cycle and usually the analogs would be back on-line and good to go. However, we are seeing a population of PACs where the power-cycling methodology
does not work well, i.e. analogs remain frozen for many power-cycles. This has become a high priority to fix!
I have looked thru the forum, LPC1788 User Manual, Eratta, etc. The links below:
Was around the earliest of being aware that we were not the only ones to discover the analog freeze problem.
A question that was posted:
Are the G120 ADC reads coming from the ADC Global Data Register (GDR), or the individual ADC Channel Registers?
ADC Channel Registers in Burst Mode
ADC Global Data Register is for trigger mode.
Seems ADC Channel Registers can handle both mode, but ADC Global Data Register is only valid in trigger mode.
Following the link chain I got to:
John_Brochue reply at end of link seems to be a good starting place for fixing the frozen analog problem?
With more reading…The errata say’s:
When using either burst mode or hardware triggering, the individual A/D Channel Data
registers should be used instead of the A/D Global Data register to read the A/D
So, we would want to use Burst mode and read individual A/D Channel Data
Is using Burst mode and reading individual A/D Channel Data registers…The way to go?
Is the G120 ADC driver source code available?
If not open source or such, is there someway (sign a doc, pay money) which allow me access to this source code?
Could we contract GHI to help in this endeavor?
Thanks…enjoy ‘Labor Day’.!