What do you think of this idea: oday I had an idea for a type of IC: Track Guard!
In high speed digital electronics there is the problem of the Race Track Condition; where the runner (or signal) in the outside lane has to run further than the runner on the inside lane.
"As an example of length mismatch tolerance, the 33 MHz PCI bus has a period of 30
nanoseconds. Of this, more than two nanoseconds is available for length mismatch. At the
speeds that signals travel in PCBs, this would allow members of the bus to be mismatched by up
to 12 inches or 60 millimeters and still work properly. A 2.5 GB/sec data bus as is employed in
the new Infiniband protocol has a period of only 400 picoseconds. The time available for length
mismatches is only 60 picoseconds. This translates into a length difference of 300 mils or 7.5
millimeters. (Obtained from online PDF: http://www.speedingedge.com/PDF-Files/busses.pdf)"
The Track Guard is simple. For each lane there is a long run of wire with a pair of PNP transistors on it. The length of the track can be electronically shortened by activating the transistor pair at that short cut. The track guard could be programmed by shift registers or by “Winning Signal” testing. Winning Signal testing functions much like a race where the opponents are stopped when one of them reaches the finish line. At the start all the lines are set to the same state (e.g. High). As the signal passes a checkpoint a flag is raised. When the first signal reaches the “finish line” the location of the other signals is noted by checking the number of checkpoints the signal managed to get past before it “lost” the race. This information is then used to configure the chip.
This chip could be useful for allowing hobby electronics persons to use high speed digital components without having to worry about the length of the signal buses. It could also be used for external Graphics Cards, Memory Arrays and CPU interconnects. In the future, ICs may employ Track Guards in package.
Usually this problem is solved by “meandering” the shorter tracks. Many EDA products have this functionality built in. Eagle, for example, does this for you automatically, if you tell it how long you want the track.
Running the signal through a transistor, especially a BJT, would cause the voltage to drop, which would be a non-starter in these sorts of protocols.
@ Pete, that’s correct but for cases where the track is actually a cable, the fold can change and the cable tolerances are off.
@ godefroi, hum you’re right. Would have to use MOSFETs instead.
Even using MOSFETs with very low RdsON, the resistance wouldn’t match between the signals anymore. I would expect it to wreak havoc.
Cables designed to carry these sorts of signals have tight tolerances. It’s why you can’t run 100GB ethernet over Cat-3 cable. Also, folding a cable doesn’t change its length.
Absolutely. Look up LVDS, Low Voltage Differential Signalling. Impedance matching matters at least as much as the length matching, because the difference in voltage IS the signal.
Specifically for LVDS, the traces are to be run as close together as possible, with a minimum of vias, using matching lengths, matching capacitances, and no 90 degree turns. Adding even a MOSFET on one of the lines would, most likely, cause it to not function at all.
The disappointing (for you) fact is, trace length matching is done on boards using traces, so there’s no need for an IC to accomplish it.
@ godefroi, LDVS would pose a problem as it would basically be an Analog system. Regarding the cabling: the Chip could implement an optional LDVS front end as an option. I’m seeing it being used to do External PCI Express lanes.
There’s already standard cables and connectors for external PCI Express: PCI Express External Cabling (also known as External PCI Express, Cabled PCI Express, or ePCIe) specifications were released by the PCI-SIG in February 2007.
Further, PCI Express uses differential signalling. Changing the voltage on one of the wires is going to affect functioning.
