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[Solved] GPIO timing in RLP



I’m using the Fez Hydra to read and write the digital IO’s as fast as possible. I use RLPlite to load a c-file compiled by Keil uVision. The c-file initializes the GPIO port in c and then toggles the port in inline assembler.

Since the processor is clocked at 200MHz and the STR assembly instruction should take 1 cycle to complete, I expected to see about 100MHz when toggling a pin in assembler (1 STR to clear and 1 STR to set the port). But I am only seeing 8,3MHz => 12 cycles per STR instruction. Am I missing something? Is this the maximum read/write speed we can achieve in the Fez Hydra? Can I disable/enable something in the c-code/assembly to speed up the processor? Will it run faster if I boot the processor from a SD-card without the NETMF?

Regards, GurraG

EDIT: I’m using PB08, pin 3 on header #3.


The peripherals do not run at 200mhz. Cash memory combined with memory speed is another reason.

If you really need to toggle pins at high speed then you may want to look into fpga instead.


Thanks for your reply, Gus!

Ok, I suspected it to be related with the memory speed, since it is located in the SDRAM. Is it possible to load the RLP procedure into SRAM to get a more predictable timing?

Otherwhise a FPGA might be the only solution for this…



Just a thought and I have no idea how hard this is, but can you write the data in parallel to the output port and use a serializer/deserializer IC to convert it to and from a serial stream?

The Hydra AT91SAM9R64 chip has 4 32bit Parallel IO ports and i’m sure it probably takes the same number of CPU ticks to write all 32 as it does just one. Hence in theory you could get a 32 times speed boost.


@ hagster - Thanks for your reply, that is a much better way to solve the problem! Why didn’t I think of that…?!



Hi again.

Just for your info, I bought a STM32F4 Discovery board and within minutes I was up and running, toggling the pins at 168MHz giving a nice square wave of 86MHz. So this should also be possible at your Cerberus boards.