Here’s the sort-of-weekly update. Firstly, given the earlier discussion of detecting design errors (dropping a device into a project type that has no driver code for that device), I thought through the Design Rules interfaces quite a bit and decided to create an extensible framework. That is, you can add new design rules (software validations and hardware design validations) by creating new VSIX extensions. Sagitta exposes it’s entire object model as VS services, and allows for extensibility using the Visual Studio extensibility model.
Design Rule violations show up in a tool window resembling the Error window in VS. One difference is that for a given rule validation failure, there can be multiple ways to mitigate that error. Expanding the error notice gives you suggested Corrective Actions, and double-clicking on any of these will take you to that diagram or code location. This is an example of a test rule’s output:
The second change was to add support for pagination on Schematic, Breadboard, and PCB diagrams (see “Page 1, Page 2, New Page” at the bottom of the editor window). That forced a bunch of breaking changes to the data model and was a bit of a soul-sucking exercise in refactoring, but it’s an essential feature that I should have thought of earlier:
You can also see the “Design Rules” output tab at the bottom left. Work continues, and I’m still on track for a first public pre-release around February.