Retun from C (RLP) to managed (C#)

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1

Hi,

i am using Hydra and want to use RLPLight.
in C code i want to send data to serial port. i succeeded to do it but have a litte problem.
for some reasons i need to disbale interrupts (CPU’s interrupts) and then i cant back to C#…
C code is:


*AT91C_AIC_IDCR  = 0xffffffff;   
*AT91C_AIC_FFDR  = 0xffffffff;   
*AT91C_AIC_ICCR  = 0xffffffff; 
	
debug_print(&startedArray[0]);
debug_print(&startedArray1[0]);


*AT91C_AIC_IDCR  = ffdr;   
*AT91C_AIC_FFDR  = ffdr;   
*AT91C_AIC_ICCR  = iccr;
return 5;

if i comment out the first 3 lines it works and returns 5, but now C doesnt return.

Do you know how can i disable all intrrupts except to “return to C#” interrupt ? which register is responsable on it and what is the value i need to give to enable only this interrupt?

2

@ shm3 - You will have to re-enable interrupts before exiting the RLP function. The execution engine which runs the managed code relies on things like the timer interrupts to handle the thread scheduling, handling of completions etc.

3

Yes, i know… i just thought that enable and diable it same register. Now i see that there are different registers for get status, for enable and for disable.
i just trying to understand the mapping between all registers.
e.g.:

#define AT91C_AIC_FFSR  (AT91_CAST(AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register

is mapping to

#define AT91C_AIC_FFER  (AT91_CAST(AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register

and to

#define AT91C_AIC_FFDR  (AT91_CAST(AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register

so i cant do this (maybe i wrong… - i am not sure)

  1. get the status:
 unsigned int ff = *AT91C_AIC_FFSR;
  1. disable it:
 *AT91C_AIC_FFDR  = 0xffffffff ;
  1. enable it again:
*AT91C_AIC_FFER = ff ;

am irgiht? will it work?

and more question:
this is mapping for fast forcing registers,what about all other?

the registers are:


// ========== Register definition for AIC peripheral ========== 
 #define AT91C_AIC_IVR   (AT91_CAST(AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
 #define AT91C_AIC_SMR   (AT91_CAST(AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
 #define AT91C_AIC_FVR   (AT91_CAST(AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
 #define AT91C_AIC_DCR   (AT91_CAST(AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
 #define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
 #define AT91C_AIC_SVR   (AT91_CAST(AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
 #define AT91C_AIC_FFSR  (AT91_CAST(AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
 #define AT91C_AIC_ICCR  (AT91_CAST(AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
 #define AT91C_AIC_ISR   (AT91_CAST(AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
 #define AT91C_AIC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
 #define AT91C_AIC_IPR   (AT91_CAST(AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
 #define AT91C_AIC_FFER  (AT91_CAST(AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
 #define AT91C_AIC_IECR  (AT91_CAST(AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
 #define AT91C_AIC_ISCR  (AT91_CAST(AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
 #define AT91C_AIC_FFDR  (AT91_CAST(AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
 #define AT91C_AIC_CISR  (AT91_CAST(AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
 #define AT91C_AIC_IDCR  (AT91_CAST(AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
 #define AT91C_AIC_SPU   (AT91_CAST(AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
4

I suspect that you have misunderstood the Fast Force Interrupt feature. I would suggest that you ignore that for now, since it sounds like all you want to do is disable/enable the interrupts. Fast Forcing is a alternative 'routing" of the interrupts, which I do not think you are really interested in.

The key registers you should be looking at are

AT91C_AIC_IECR -> Write 1s to enable the corresponding interrupts
AT91C_AIC_IDCR -> Write 1s to disable the corresponding interrupts
AT91C_AIC_IMR -> Mask indicating which interrupts are currently enabled (1s) or disabled (0s)

The Status Registers (AT91C_AIC_ISR/FFSR) indicate if the interrupt is currently triggered.

For more detail you can read chapter 29 of the data sheet for the processor.

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