That is how the code was, didn’t change.
If I understand the code correctly then it loads the address of the stack into r0, then it loads that pointer from r0 into sp. This sets up the stack location…
Yes,but the order for the MOV should be sp,r0 not r0,sp.
Ahh, yes, it was code that I changed… 
Was one of those annoying “lo register required” errors… :-[
Now it runs a lot further. I get here:
.section i.FAULT_SubHandler, "xa", %progbits
@ AREA ||i.FAULT_SubHandler||, CODE, READONLY
FAULT_SubHandler:
@ on entry, we have an exception frame on the stack:
@ SP+00: R0
@ SP+04: R1
@ SP+08: R2
@ SP+12: R3
@ SP+16: R12
@ SP+20: LR
@ SP+24: PC
@ SP+28: PSR
Going to be fun trying to figure out WHY I get there…
Good!
By the way what is the top of your FirstEntry.s looks like.Is it something like this:
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
@
@ Licensed under the Apache License, Version 2.0 (the "License");
@ you may not use this file except in compliance with the License.
@ You may obtain a copy of the License at http:;www.apache.org/licenses/LICENSE-2.0
@
@ Copyright (c) Microsoft Corporation. All rights reserved.
@ Implementation for STM32: Copyright (c) Oberon microsystems, Inc.
@
@ CORTEX-M3 Standard Entry Code
@
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
.global EntryPoint
.global PreStackInit_Exit_Pointer
.global ARM_Vectors
.global StackBottom
.global StackTop
.global HeapBegin
.global HeapEnd
.global CustomHeapBegin
.global CustomHeapEnd
.extern PreStackInit
.ifdef HAL_REDUCESIZE
.extern BootEntryLoader
.else
.extern BootEntry
.endif
.extern BootstrapCode
@ PRESERVE8
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
.section SectionForStackBottom, "a", %progbits
StackBottom:
.word 0
.section SectionForStackTop, "a", %progbits
StackTop:
.word 0
.section SectionForHeapBegin, "a", %progbits
HeapBegin:
.word 0
.section SectionForHeapEnd, "a", %progbits
HeapEnd:
.word 0
.section SectionForCustomHeapBegin, "a", %progbits
ARM_Vectors:
.space 84*4 @ exception vector table (max 84 entries)
CustomHeapBegin:
.word 0
.section SectionForCustomHeapEnd, "a", %progbits
CustomHeapEnd:
.word 0
.section i.EntryPoint, "xa", %progbits
.thumb
EntryPoint:
@ The first word has several functions:
@ - It is the entry point of the application
@ - it contains a signature word used to identify application blocks
@ - out of reset it contains the initial stack pointer value
@ - it is the first entry of the initial exception handler table
@ The actual word used is 0x2000E00C
.byte Start @ 0xE00C
.hword 0x2000 @ Booter signature is 0x2000E00C
.word Start @ Reset
.word Fault_Handler @ NMI
.word Fault_Handler @ Hard Fault
.word Fault_Handler @ MMU Fault
.word Fault_Handler @ Bus Fault
.word Fault_Handler @ Usage Fault
Start:
@ allow per processor pre-stack initialization
....
Still trying to figure out issues I am having with linker
I think this is your problem:
.byte Start @ 0xE00C
It can’t be byte, must be .hword?
Anyway, I had problems with that code. Looks like the F4 wants the first entry to be the start address so I changed that to have the Start address if the first two…
Here is my full file:
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
@
@ Licensed under the Apache License, Version 2.0 (the "License")@
@ you may not use this file except in compliance with the License.
@ You may obtain a copy of the License at http:@ www.apache.org/licenses/LICENSE-2.0
@
@ Copyright (c) Microsoft Corporation. All rights reserved.
@ Implementation for STM32: Copyright (c) Oberon microsystems, Inc.
@
@ CORTEX-M3 Standard Entry Code
@
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
.global EntryPoint
.global PreStackInit_Exit_Pointer
.global ARM_Vectors
.global StackBottom
.global StackTop
.global HeapBegin
.global HeapEnd
.global CustomHeapBegin
.global CustomHeapEnd
.extern PreStackInit
.ifdef HAL_REDUCESIZE
.extern BootEntryLoader
.else
.extern BootEntry
.endif
.extern BootstrapCode
@ PRESERVE8
@ *************************************************************************
.section SectionForStackBottom, "a", %progbits
StackBottom:
.word 0
.section SectionForStackTop, "a", %progbits
StackTop:
.word 0
.section SectionForHeapBegin, "a", %progbits
HeapBegin:
.word 0
.section SectionForHeapEnd, "a", %progbits
HeapEnd:
.word 0
.section SectionForCustomHeapBegin, "a", %progbits
CustomHeapBegin:
ARM_Vectors: .space 84*4 @ exception vector table (max 84 entries)
.section SectionForCustomHeapEnd, "a", %progbits
CustomHeapEnd:
.word 0
.section i.EntryPoint, "xa", %progbits
EntryPoint:
@ The first word has several functions:
@ - It is the entry point of the application
@ - it contains a signature word used to identify application blocks
@ - out of reset it contains the initial stack pointer value
@ - it is the first entry of the initial exception handler table
@ The actual word used is 0x2000E00C
@ .section .text.Reset_Handler
@ .weak Reset_Handler
@ .type Reset_Handler, %function
@ b Start @ 0xE00C
@ .word 0x2000 @ Booter signature is 0x2000E00C
.word Start @ Reset
.word Start @ Reset
.word Fault_Handler @ NMI
.word Fault_Handler @ Hard Fault
.word Fault_Handler @ MMU Fault
.word Fault_Handler @ Bus Fault
.word Fault_Handler @ Usage Fault
Start:
@ allow per processor pre-stack initialization
PreStackEntry:
b PreStackInit
PreStackInit_Exit_Pointer:
ldr r0,=StackTop
mov sp,r0
bl BootstrapCode
.ifdef HAL_REDUCESIZE
b BootEntryLoader
.else
b BootEntry
.endif
@ ALIGN 4
StackTop_Ptr:
.word StackTop
Fault_Handler:
b Fault_Handler
.end
Forgive my last reply.
It should be:
mov sp, r0
@ Errol
Try this one:
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
@ Licensed under the Apache License, Version 2.0 (the "License");
@ you may not use this file except in compliance with the License.
@ You may obtain a copy of the License at http:;www.apache.org/licenses/LICENSE-2.0
@
@ Copyright (c) Microsoft Corporation. All rights reserved.
@ Implementation for STM32: Copyright (c) Oberon microsystems, Inc.
@
@ CORTEX-M3 Standard Entry Code
@
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
.global EntryPoint
.global PreStackInit_Exit_Pointer
.global ARM_Vectors
.global StackBottom
.global StackTop
.global HeapBegin
.global HeapEnd
.global CustomHeapBegin
.global CustomHeapEnd
.extern PreStackInit
.ifdef HAL_REDUCESIZE
.extern BootEntryLoader
.else
.extern BootEntry
.endif
.extern BootstrapCode
@ PRESERVE8
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
.section SectionForStackBottom, "a", %progbits
StackBottom:
.word 0
.section SectionForStackTop, "a", %progbits
StackTop:
.word 0
.section SectionForHeapBegin, "a", %progbits
HeapBegin:
.word 0
.section SectionForHeapEnd, "a", %progbits
HeapEnd:
.word 0
.section SectionForCustomHeapBegin, "a", %progbits
ARM_Vectors:
.space 84*4 @ exception vector table (max 84 entries)
CustomHeapBegin:
.word 0
.section SectionForCustomHeapEnd, "a", %progbits
CustomHeapEnd:
.word 0
.section i.EntryPoint, "xa", %progbits
.thumb
EntryPoint:
@ The first word has several functions:
@ - It is the entry point of the application
@ - it contains a signature word used to identify application blocks
@ - out of reset it contains the initial stack pointer value
@ - it is the first entry of the initial exception handler table
@ The actual word used is 0x2000E00C
b Start @ 0xE00C
.hword 0x2000 @ Booter signature is 0x2000E00C
.word Start @ Reset
.word Fault_Handler @ NMI
.word Fault_Handler @ Hard Fault
.word Fault_Handler @ MMU Fault
.word Fault_Handler @ Bus Fault
.word Fault_Handler @ Usage Fault
Start:
@ allow per processor pre-stack initialization
PreStackEntry:
b PreStackInit
PreStackInit_Exit_Pointer:
ldr r0, StackTop_Ptr
mov sp, r0
bl BootstrapCode
.ifdef HAL_REDUCESIZE
b BootEntryLoader
.else
b BootEntry
.endif
@ .align 4
StackTop_Ptr:
.word StackTop
Fault_Handler:
b Fault_Handler
@ .thumb
.end
Might be wrong, but that first word (0x2000E00C) still doesn’t do it for me.
From what I understand, it sets the stack pointer so should not affect start-up.
I have done more investigating…
It gets quite far. I need to hook a serial port up to the board. Looks like it gets to “CLR Running…”.
But this only happens while i’m stepping the code. When I run it then it doesn’t work… :(. It either ends up in Fault_Handler or in Sub_Fault_Handler.
Might be something with ISR or watchdog…
Yeah I am using 4.5, so it looks like it is a little bit different. By the way what did you end up using for
SmartPtr_cortex.cpp translation?
4.5? What is that in reference to?
This is my SmartPtr_cortex file. The problem might be in there somewhere…
#else //#ifndef __GNUC__
#pragma arm section code = "SectionForFlashOperations"
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) Microsoft Corporation. All rights reserved.
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#include <tinyhal.h>
//--//
//--//
//--//
///////////////////////////////////////////////////////////////////
// For Thumb2 code, we need to declare some functions as extern
// and implement them in assembly, as the RVDS3.1 compiler does
// not support inline assembly
//
//
//
///////////////////////////////////////////////////////////////////
SmartPtr_IRQ::SmartPtr_IRQ(void* context)
{
m_context = context;
Disable();
}
SmartPtr_IRQ::~SmartPtr_IRQ()
{
Restore();
}
BOOL SmartPtr_IRQ::WasDisabled()
{
return (m_state & 0x3) == 0x3;
}
void SmartPtr_IRQ::Acquire()
{
UINT32 Cp = m_state;
if((Cp & 0x3) == 0x3)
{
Disable();
}
}
void SmartPtr_IRQ::Release()
{
if((m_state & 0x3) == 0)
{
asm("LDR r1,=0xE000E180;");
asm("LDR r0,[r1];");
asm("LDR r1,=0xE000E100;");
asm("LDR r2,=0x3;");
asm("STR r2,[%0];":"=r"(m_state));
asm("BX LR;");
}
}
void SmartPtr_IRQ::Probe()
{
UINT32 Cp = m_state;
if((Cp & 0x3) == 0)
{
asm(
"LDR r1,=0xE000E100;"
"LDR r0,[r1];"
"LDR r2,=0x3;"
"STR r2,[r1];"
"STR r0,[r1];"
"BX LR ;"
);
}
}
BOOL SmartPtr_IRQ::GetState(void* context)
{
bool ret;
asm("LDR r1,=0xE000E300");
asm("LDR r0,[r1]");
asm("AND r0,r0,#0x3":"=r"(ret));
asm("BX LR");
}
BOOL SmartPtr_IRQ::ForceDisabled(void* context)
{
bool ret;
asm("LDR r1,=0xE000E180");
asm("LDR r0,[r1]");
asm("AND r0,r0,#0x3");
asm("LDR r2,=0x3");
asm("STR r2,[r1]":"=r"(ret));
asm("BX LR");
return ret;
}
BOOL SmartPtr_IRQ::ForceEnabled(void* context)
{
bool ret;
asm("LDR r1,=0xE000E180;");
asm( "LDR r0,[r1];");
asm("AND r0,r0,#0x3;");
asm("LDR r1,=0xE000E100;");
asm("LDR r2,=0x3;");
asm("STR r2,[r1];":"=r"(ret));
asm("BX LR;");
return ret;
}
void SmartPtr_IRQ::Disable()
{
asm("LDR r0,=0xE000E180");
asm("LDR r1,=0x3");
asm("STR r1,[r0]":"=r"(m_state));
asm("BX LR");
}
void SmartPtr_IRQ::Restore()
{
asm("LDR r0,=0xE000E100");
asm("LDR r1,=0x3");
asm("STR r1,[r0]":"=r"(m_state));
asm("BX LR");
}
#endif
Please note: I had to make some changes to my linker file. The code was tring to init the ram, but thought that it was at address 0x00000000. I also updated the ram sizes and stack locationd for my 128KB chip. Once I can figure out where the Closely Coupled Ram sits, then I’ll move the stack and heap there, then the app can have the full 128KB ram…
Bummer, seems that I don’t have the new scatter file with me. :-[
GCC toolchain version.
I have tried both without much changing…
This sucks. My codesourcery GCC license has just expired. 
Are you not using the free edition?
I have installed the 30 day trail just to see if I can import the ELF into it’s IDE. Didn’t work. Ended up using plain Eclipse with GDB addons + Atolic STM32 GDB server. Works most of the time…
Ah,yes found the free version. Back to normal now. Thanks
Here is my version of the SmartPtr translation. It is one method, but they all look alike.
void SmartPtr_IRQ::Release()
{
/*
Restore();
*/
asm("LDR r1,[r0,%0]" :: "i" (offsetof(SmartPtr_IRQ, m_state)));
asm("MSR PRIMASK,r1");
asm("BX lr");
}
One strange thing (bug) I have noticed is that asm(“BX lr”) generates two BX instruction. For example the above function ends up like this:
08006b96 <_ZN12SmartPtr_IRQ7ReleaseEv>:
8006b96: 6801 ldr r1, [r0, #0]
8006b98: f381 8810 msr PRIMASK, r1
8006b9c: 4770 bx lr
8006b9e: 4770 bx lr
Any thoughts?
You should give GCC 4.6.2 a try.
It’s the latest you can get from code sourcery, they have made some major changes for the cortex M4.
[url]https://sourcery.mentor.com/sgpp/lite/arm/portal/release1802[/url]
I would love too. The link you have provided is the latest for the free - Lite edition (I am using it right now). Unfortunately that one is 4.5.2.
Figured that one out myself. ;D. Last BX is part of the compiler generated epilogue. To avoid that the method has to be marked with naked attribute in the header file like this:
void Acquire() __attribute__ ((naked));
this has to be “ifdefed” for GCC and possibly Cortex or ST32 to maintain compatibility with the rest of the porting kit.
hmm, i thought it “generates” two statements because the command needs two full words of flash, one for the command and one for a full 32 bit address.
That was how the PIC cpus did it though, only with 12/14 bits per command instead of 32 bits…