LCD clock output

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1

Hi all,

I’ve posted this on a couple of other places but thought I might be able to find some boffins in here who would lend some further information on this as so far I have not found an answer for this that explains it.

I discovered this on an ARM Cortex A7 embedded board but have since checked the output from the G120 and it exhibits the same behavior as I am seeing on the ARM Cortex core.

I am using the same RGB type output as the G120 and all of the R,G,B, DE, HSYNC and VSYNC are all a nice clean 0 to 3.3V swing with nice clean square edges.

The clock on the other hand is not and swings from 1 to 1.8 volts. Not what I was expecting and confusing me to where in the clock timing the edge is sampled. According to the LCD the data is sampled on the falling edge of the clock but with a nice sine wave you can see in the attached image (that is a 33Mhz clock) it doesn’t meet the LCD voltage limit of 0.9 volts for the low detection (0.3 Vdd)

I have an issue when on low battery voltage but after further checks may not be related to the clock although timing edge detection could occur, I am more interested to know why the clock is a sine wave and not a square or at least with the same voltage swing as I would expect it to be?

2

Wild guess here, but capacitance in the traces? 33 MHz might be high enough that it could be a factor?

3

That was a thought as was the probe and scope bandwidth.

The LCD data for R, G and B is clocked in at the same rate as the DCLK and they are nice and clean with a 0 to 3.3V swing.