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Hydra firmware source


#1

Hi.

I’m dealing with a problem here - as I start the Hydra, it sets all pins to 1 and outputs 3.3v. I need it to be 0 by default.
Currently I’m resetting the pins to 0 in C# code but on reset it still holds 1 till it gets to my code.
I understand that this is set in Hydra’s FW, that all GPIO’s will be set to 1 by default. Is there any way to set it to 0 by default? Hydra is open source (correct me if I’m wrong) so may be I could tweak the FW and to get it write? Where can I get the source for Hydra’s FW?

Thanks.


#2

Here is the link for the source code:

http://ghiopensource.codeplex.com/

You can also add pull-down resistors for the pins you want to be low on start-up.


#3

In addition to the info @ Architect has provided, you can use the following document as a guide to building the Hydra firmware.

http://www.ghielectronics.com/docs/130/firmware-custom-build-fez-hydra


#4

All the pins are set to inputs with pullup.

If you add a pull down resistor of, say, 10K, then you should be ok…


#5

Thanks. Will take a look at it and update you guys!


#6

Some more interesting questions - all GPIO lines are working at 3.3v I/O by default.

  1. Will Hydra by default consider 1.8v input as 1?

  2. Is it possible to set default 1 as 1.8v for input AND output? I understand that if it’s possible (using EBI register), it should be done in the FW on boot, but will this also require some HW rework?

  3. Will the move to 1.8v hurt PIO performance?


#7

I would check the processor datasheet for exact voltage levels.


#8

Here’s what I’ve found in CPU’s spec:


5.2 Programmable I/O Lines Power Supplies
The power supplies pins VDDIOM support two voltage ranges. This allows the device to reach
its maximum speed either out of 1.8V or 3.3V external memories.
The maximum speed is MCK on the pin SDCK (SDRAM Clock) loaded with 30pF for power supply
at 1.8V and 50 pF for power supply at 3.3V.
The maximum speed on the other signals of the External Bus Interface (control, address and
data signals) is 50 MHz.
The voltage ranges are determined by programming registers in the Chip Configuration registers
located in the Matrix User Interface.
At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either
1.8V or 3.3V. The user must make sure to program the EBI voltage range before getting the
device out of its Slow Clock Mode.
The PIO lines are supplied through VDDIOP and the speed of the signal that can be driven on
them can reach 50 MHz with 50 pF load.

So it seems I need to configure that EBI register. I’m not good enough in electronics so not sure I understand it all right.

Now that EBI register is providing the next bit for configuration:


VDDIOMSEL: Memory voltage selection
0 = Memories are 1.8V powered.
1 = Memories are 3.3V powered.

So it allows me to configure memory voltage. It’s not really helping as memory voltage is HW requirement and I’m 99% that given memory on Hydra will not work on 1.8v and I also can’t see how it will affect my Parallel I/O voltages.


#9

We use 3.3v memory. You need to see what the high and low levels when using 3.3v


#10

Looks like it’s 3.3v. Couldn’t find anything about changing it to 1.8v


#11

you can’t change it to 1.8v but what I was trying to say is that you can look at datasheet to see what expected levels are. I am near positive 1.8v will not work.


#12

Step back Stargazer, what is it you’re trying to achieve?

From the datasheet http://www.atmel.com/Images/doc6221.pdf when the processor is running on 3.0v or above (Vddio of 3v0 to 3v6) you need a minimum of 2v0 to be recognised as a high signal. So that means, you will not have any success with 1v8


#13

Well, I have I2C line with 1.8v which I’m connecting to as a slave device (I2C slave implemented in code by bit banging, not using the embedded one in the HW, running in RLP mode). I also have a few GPIO lines for interrupts which are also should be 1.8v.


#14

If the device you have isn’t 3v3 tolerant (check the datasheet) then you might get away with just a voltage divider resistor network for your output pins, but input pins will require a level shifter for the input pins.


#15

Well, it looks like this is what I’ll have to do.
Thanks for the help guys!