Is it really not possible to set any port on the FEZ as an Output Open Drain?
Is it just this board or TinyCLR in general that doesn’t support it?
Im kind of surprised.
Does the processor support it? It is something we can definitely look into.
Well I suppose there must be exceptions but In my personal yet limited experience, every mcu i have ever used supports it.
Confirming with the STM32F401RE data sheet, section 3.27 summarizes…
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 84 MHz.
Otherwise as in the case of this processor, your limited to around 25mA drain per pin, 120mA total, and then only at VDD, which is very limiting. So something that is so commonly used, that can simply be taken care on the die with few transistors is a no brainer…
So how long would it take to add support?