G30HDR Interrupt port

Page 26 of manual G30 SoC User Manual
Interrupt Pins
Note: Only pins on port 0 and port 2 are interrupt capable.

What are/is port 0 and 2?

How do I relate this to specific cpu pins?
Or can you tell me which if any are interrups


Do you have a link to that “User Manual” ?

@ Architect -

I think it is the same one.

@ willgeorge - I think this is a copy/paste error from G120 User Manual.

All pins on G30 are interrupt capable, but there are 16 interrupt channels that are shared by the pins of the same number.
I.e. PA1, PB1, PC1, etc share the same channel so you can’t have Interrupt enabled on PA1 and PB1 at the same time.

@ Architect -

Thank You… The ports statement got me confused,

@ willgeorge - You are welcome!

I have created Task Tracker item to correct the manual.


All these documents are obsolete. The new datasheets should be live this week. Blame Gary for the delay.

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Dodgy guy, always thought so. :wink: . (I’m on enough lists thanks, so I refuse your offer to add me to another :slight_smile: )

@ Gus - That was the User Manual not Datasheet. Are you guys making new User Manuals as well?

No need for manuals, more on this later on today.

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