Seeing as there is still no info on frequency I have to assume 20kHz.
That means that you must sample at 40kHz per channel, a total of 240000 samples per second over 6 channels. The chip supports a theoretical max of 400000 samples per second, total.
You will need to do one multiplication, one addition and one subtraction per sample:
240000 multiplications per second.
240000 additions per second
240000 subtractions per second.
Total: 720000 inscructions per second.
This will give you 100 cpu cycles per instruction. I can’t see from the spec how many CPU cycles are required for one multiplication command.
The ARM7TDMI, which this chip is based on, looks like it does support the compount Multiply And Accumulate instruction.
This might be possible, if you do everything in c++ using RLP, and never yield control back to the MicroFramework, of if you wipe the Panda and just use C++/assembler.
Edit: simulating paralel processing doesn’t help in any way. Paralel processing helps because there are several CPUs working together to speed up the calculations. You can’t simulate 10 CPUs using one CPU and expect to get the processing power of 10 CPUs, because there is still only one CPU doing the work.