Cerbuino bee RLP lite

Archive
#1

Hi

What are the Base R/0 and R/W addresses for Cerbuino Bee?
The RLP lite example does not help (me):

[em]Linkage Settings

For FEZ Hydra, in the text field R/O Base: address 0xA0000000
R/W Base: 0xA0080000. These addresses are the locations on FEZ Hydra that has been reserved for executing RLPLite functions. The total memory allocation is one megabyte (0x100000) at address base 0xA0000000.

The FEZ Cerberus family has two different deployment regions depending on which firmware is used:
…
For the Non Ethernet firmware, the region is 8KB (0x2000) and begins at address 0x20000000.[/em]

I am assuming that the R/O address is 0x2000 but what is R/W?

Thanks!!

#2

Sorry, I meant

“I am assuming that the R/O address is 0x20000000 but what is R/W?”

#3

The RLP for any board has a certain amount of memory put aside for the native code. The R/O and R/W regions are actually dependent on the program that you create. Some programs require more R/O than R/W and may be more R/W than R/O. Your compiler will give warning or errors depending on these needs.

The Hydra’s RLP regions are only defined in the example you reference because that was what was used. The regions can be sized to your needs. The typical rule of thumb that I personally use is split the R/O and R/W in half. If you need more or less (because your compiler may inform you of memory overlap), you can easily adjust to provide the necessary memory space.

#4

On my FEZ Cerberus Mainboard, these settings worked fine:

R/O Base: 0x20000000
R/W Base: 0x20002000

#5

Thank you both Danibjor and Aaron.

I still don’t get something though:

From the GHI site RLP lite docu:
For FEZ Hydra, in the text field R/O Base: address 0xA0000000
R/W Base: 0xA0080000. These addresses are the locations on FEZ Hydra that has been reserved for executing RLPLite functions. The total memory allocation is one megabyte (0x100000) at address base 0xA0000000.

OK, given what Aron said that looks to me as if in this case the R/W will (could) go from 0xA0000000 to 0xA007FFFF, and the R/O will go from 0xA0080000 to 0xA00FFFFF.

If this is correct, it would mean to me that for the Cerberus it should be set for instance to:

For the Non Ethernet firmware, the region is 8KB (0x2000) and begins at address 0x20000000.
-> R/O = 0x20000000
R/W = 0x20001000 to split the range in half.

danibjor, I am not sure how you can set the R/W base to 0x20002000. It seems to me you have used up all the memory available with R/O

Another stupid question: Why does the RLP lite example choose the AT91SAM9RL64 MCU as the target for Keil? I don’t understand the significance.

Thanks a lot

#6

@ eribla - using those addressees in Keil worked fine on my project.

I changed the CPU to get the correct settings. Look on the product page, when you hold your mouse over the CPU, it tells you the model number. You’ll find that number back in the list in Keil.

Edit: CPU -> MCU