Is the SPI3 on this document mistakenly labeled as SPI1?
[url]http://www.ghielectronics.com/downloads/schematic/FEZ_Cerb40_II_SCH.pdf[/url]
The pins in question are : PB3, PB4 and PB5
Not to the best of my knowledge.
https://www.ghielectronics.com/docs/44/fez-cerb40-developer shows SPI1 as well (and I trust that document, it’s obsolete! 
)
Therefore the schematics sheet is wrong.
@ Mr. John Smith - What are you talking about with SPI3? A search of the document shows no SPI3 bus. How is it wrong? The pins you are referring are SPI1_SCK, SPI1_MISO, and SPI1_MOSI respectively.
Agree Aron, theres no SPI3 I could find either?
the µC has 3 SPI buses. The datasheet (for the micro) says those pins are for SPI3, but they are labeled as SPI1. Then there is a second set of SPI1 pins labeled on the other side.
firmware mapping versus what the processor calls them is irrelevant though. For you, they are SPI1.
So then there are 2 sets of SPI1 Pins? One set on each side of the µC?
To Illustrate my point.
This is some confusing schematic! :
so please be explicit - CERB40 or CERB40 II ?
The developers guide is the important thing to leverage… https://www.ghielectronics.com/docs/44/fez-cerb40-developer is the one I quoted before, and I treat as gospel, so the PBx pins are SPI1, and PAx pins are not SP! (the text label on additional features on those pins is not correct). Gus will confirm that shortly
@ Brett - Aron is the right person to clear all this up.
It’s under the Cerb40II resources section, the Schematic PDF
https://www.ghielectronics.com/catalog/product/450
http://www.ghielectronics.com/downloads/schematic/FEZ_Cerb40_II_SCH.pdf
Ha, this one took me by surprise:
The tool tip for the 9 analogue in is visible when the page first loads! For I sec I though 912 bit resolution! Egad!
so again, you’re interested in Cerb40II ??
The schematic is wrong. The PAx pin items are not SPI pins. The Cerb40 developers guide (bible) is accurate. Aron will confirm since Gus ceded the throne to him
@ Brett - Yes, I’m interested in the Cerb40II