Gus, you said that we only need to ask ( http://www.tinyclr.com/forum/topic?id=7917&page=8#msg86838 ), so here’s the question: when will we be able to get Cerb40 boards with the correct loading capacitors for the LSE crystal?
2 things, we make things in high volume in order to get you things at lower cost. This means the next batch is months away. Second, we do not change BOM after product ship without changing the version number, which means a new pcb with new version. This also means the next batch.
With that being said, how many do you need with correct capacitors?
Two, maybe three, over the next months.
If you only need couple and you will need to solder crystal, power supply and other solder-related work anyway then changing the caps is minor compared to the rest. But of course, this will be taken care of on next bach.
Thanks for the info.
Has a final decision been made on exactly what the caps get replaced with? Last I remember there was debate over exactly what values are appropriate.
The datasheet isn’t 100% clear on the issue, and ST won’t really respond to us little people. GHI could get a definite response from them, I would guess.
We will try to ping them and hopefully we will get an answer. Do you know what page and what document we should point them to?
Gus, forgive my frustration here, but we’ve been over and over and over this. For example:
Specifically, page 93 of the datasheet says:
The datasheet refers you to AN2867, which (on page 19) lists a bunch of recommended parts, all with CL of either 6 or 7 pF.
So looks like there is an answer in datasheet so why contact ST? I did see you post about this multiple times and I still do not understand the problem.
You’re still recommending 12.5 pF crystals on the wiki page, and your new board revision has 18 pF load capacitors, despite the very specific maximum given in the datasheet. That’s the problem.
Let me share some thoughts on this
The CL for a crystal is determined by the crystal and NOT by the MCU. So if the same crystal were to be used on different MCUs designs the CL remains same. If you need more information you have to talk to the crystal vendor NOT to the MCU vendor.
Most often the crystal vendor has factory trimmed the crystal using capacitance values specified by CL.
Second if the capacitors have been connected in parallel on the design (I have not cross checked the Cerb40 schematic), it is actually in series from the perspective of the crystal
so the effective parallel load of the 12.5pf crystal is 6.25pf. This is within spec. of the ST AN2867. In reality you need to add 1 -5 pf for stray capacitance and pin capacitance. If the capacitance is a little higher than the recommend 7pf it may drive up teh frequency, this will actually be hundred parts per million.
Temperature of the crystal also plays a role here. You need to experiment with different values to match the actual crystal usage ambient conditions, capacitor tolerance and board layout. Depending on what error rate you are shooting for this will vary. For higher accuracy try using an temperature compensated oscillator or PLL or a silicon based solution (try Maxim or Cypress).
Why, then, does the datasheet give maximum values for CL1 and CL2, if the MCU doesn’t care?
GHI does not recommend any value, please consult STM32 datasheet and the crystal datasheet.