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Cerb40 II -- Effect Of Continuous GPIO Pin Voltage When SoM Powered Down


#1

A question for the Oracle(s)…

I’m powering a portable Cerb40 II based project from a LiPoly battery and power-management breakout board combo (not mentioning the make/model here as it’s non-GHI and thus not cricket) and would like to include detection of a low-power state. A low battery indicator is available from the power management board (1=OK, 0=LowBatt)…I plan to include the ability to power the Cerb40 II (and thus the entire project) down via on/off control also provided by the power manager, this to conserve power and also to allow power/programming via Verb’s USB port.

This is all grounder-type stuff and I wouldn’t waste your time, but…

A careful pre-wireup study of the power board shows that the low-batteryh indicator ALWAYS reflects the battery state, even when the power board is in the “off” state (presumably low-battery trumps “off” in their world).

THE QUESTION (finally!): When the Cerb40 II is powered down, is continuous application of this battery state (a legal voltage [0…5V]) to a GPIO pin going to damage the STM32 or anything downstream from it? If so, is there a universal way of adding external protection (other than a separate physical switch… cringe) to prevent problems?

Looking forward to your wisdom on this…

Thanx…


#2

If I understand this correctly, add a large resistor in series, like 100k, and you should be fine.


#3

Gus…

Quick on the draw and right on target at ever… best damn forum support anywhere…

Thanx much…

GEB