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2 fez 1 sram


#1

I thought I would see how well SPI SRAM works when shared. The Mini is writing to the SRAM and the Panda is reading it to display. There is no direct communication so they just wait for the CS line to be free before using it. The gates are slow at 3V so the max speed would be 3Mhz and it’s stable at 2Mhz.


#2

This is cool! What SRAM do you use?


#3

I love how you always add hardware to improve software.


#4

It’s the 23K256. This seemed like the easiest way to have some form of DMA.

It would just need the AND chip if I could get it to work with the idle clock held high. If it’s possible to automatically invert the SPI data then everything can just use the NAND chip. The 4th NAND gate could invert it but the speed would have to drop to 1Mhz because of the extra delay.